Search

Lam T. Mai

Examiner (ID: 13914)

Most Active Art Unit
2845
Art Unit(s)
2819, 2845
Total Applications
2568
Issued Applications
2446
Pending Applications
84
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7273572 [patent_doc_number] => 20040233023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-25 [patent_title] => 'In line structure for agitation of fluid dielectrics in RF devices' [patent_app_type] => new [patent_app_number] => 10/441743 [patent_app_country] => US [patent_app_date] => 2003-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4195 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0233/20040233023.pdf [firstpage_image] =>[orig_patent_app_number] => 10441743 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/441743
In line structure for agitation of fluid dielectrics in RF devices May 18, 2003 Issued
Array ( [id] => 969091 [patent_doc_number] => 06940369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Surface acoustic wave device having excellent balancing characteristics between balanced terminals and a communication device using the same' [patent_app_type] => utility [patent_app_number] => 10/438919 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 30 [patent_no_of_words] => 7592 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940369.pdf [firstpage_image] =>[orig_patent_app_number] => 10438919 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438919
Surface acoustic wave device having excellent balancing characteristics between balanced terminals and a communication device using the same May 15, 2003 Issued
Array ( [id] => 6768483 [patent_doc_number] => 20030214423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Circuit and method for DC offset calibration and signal processing apparatus using the same' [patent_app_type] => new [patent_app_number] => 10/438941 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7696 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20030214423.pdf [firstpage_image] =>[orig_patent_app_number] => 10438941 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438941
Circuit and method for DC offset calibration and signal processing apparatus using the same May 15, 2003 Issued
Array ( [id] => 7409804 [patent_doc_number] => 20040227581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Monolithic nonlinear transmission lines and sampling circuits with reduced shock-wave-to-surface-wave coupling' [patent_app_type] => new [patent_app_number] => 10/439563 [patent_app_country] => US [patent_app_date] => 2003-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3302 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0227/20040227581.pdf [firstpage_image] =>[orig_patent_app_number] => 10439563 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/439563
Monolithic nonlinear transmission lines and sampling circuits with reduced shock-wave-to-surface-wave coupling May 15, 2003 Issued
Array ( [id] => 7626329 [patent_doc_number] => 06768434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-27 [patent_title] => 'High speed x/sine(x) correction circuit' [patent_app_type] => B1 [patent_app_number] => 10/440342 [patent_app_country] => US [patent_app_date] => 2003-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1588 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/768/06768434.pdf [firstpage_image] =>[orig_patent_app_number] => 10440342 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/440342
High speed x/sine(x) correction circuit May 14, 2003 Issued
Array ( [id] => 1218661 [patent_doc_number] => 06707343 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-16 [patent_title] => 'Frequency synthesis apparatus, systems, and methods' [patent_app_type] => B2 [patent_app_number] => 10/438081 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5737 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/707/06707343.pdf [firstpage_image] =>[orig_patent_app_number] => 10438081 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/438081
Frequency synthesis apparatus, systems, and methods May 13, 2003 Issued
Array ( [id] => 6768380 [patent_doc_number] => 20030214320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Semiconductor device and manufacturing method for the same' [patent_app_type] => new [patent_app_number] => 10/437391 [patent_app_country] => US [patent_app_date] => 2003-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5617 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20030214320.pdf [firstpage_image] =>[orig_patent_app_number] => 10437391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/437391
Semiconductor device and manufacturing method for the same May 13, 2003 Issued
Array ( [id] => 1184332 [patent_doc_number] => 06737998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-18 [patent_title] => 'Method and device for correcting signal' [patent_app_type] => B1 [patent_app_number] => 10/436041 [patent_app_country] => US [patent_app_date] => 2003-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3723 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/737/06737998.pdf [firstpage_image] =>[orig_patent_app_number] => 10436041 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/436041
Method and device for correcting signal May 11, 2003 Issued
Array ( [id] => 7358229 [patent_doc_number] => 20040004504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Control of guard-flops' [patent_app_type] => new [patent_app_number] => 10/434092 [patent_app_country] => US [patent_app_date] => 2003-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5700 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004504.pdf [firstpage_image] =>[orig_patent_app_number] => 10434092 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/434092
Control of guard-flops May 8, 2003 Issued
Array ( [id] => 976344 [patent_doc_number] => 06933748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-23 [patent_title] => 'Filter network combining non-superconducting and superconducting filters' [patent_app_type] => utility [patent_app_number] => 10/430914 [patent_app_country] => US [patent_app_date] => 2003-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4126 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/933/06933748.pdf [firstpage_image] =>[orig_patent_app_number] => 10430914 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/430914
Filter network combining non-superconducting and superconducting filters May 5, 2003 Issued
Array ( [id] => 1050971 [patent_doc_number] => 06861871 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-01 [patent_title] => 'Cascaded logic block architecture for complex programmable logic devices' [patent_app_type] => utility [patent_app_number] => 10/428885 [patent_app_country] => US [patent_app_date] => 2003-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4935 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/861/06861871.pdf [firstpage_image] =>[orig_patent_app_number] => 10428885 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428885
Cascaded logic block architecture for complex programmable logic devices Apr 30, 2003 Issued
Array ( [id] => 988523 [patent_doc_number] => 06922078 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-07-26 [patent_title] => 'Programmable logic device with enhanced wide and deep logic capability' [patent_app_type] => utility [patent_app_number] => 10/428982 [patent_app_country] => US [patent_app_date] => 2003-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 4608 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/922/06922078.pdf [firstpage_image] =>[orig_patent_app_number] => 10428982 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428982
Programmable logic device with enhanced wide and deep logic capability Apr 30, 2003 Issued
Array ( [id] => 6820398 [patent_doc_number] => 20030218559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-27 [patent_title] => 'A/D converter circuit and current supply circuit' [patent_app_type] => new [patent_app_number] => 10/426636 [patent_app_country] => US [patent_app_date] => 2003-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 38849 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0218/20030218559.pdf [firstpage_image] =>[orig_patent_app_number] => 10426636 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426636
A/D converter circuit and current supply circuit Apr 30, 2003 Issued
Array ( [id] => 1057223 [patent_doc_number] => 06856164 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Semiconductor integrated circuit having on-chip termination' [patent_app_type] => utility [patent_app_number] => 10/426687 [patent_app_country] => US [patent_app_date] => 2003-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2547 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/856/06856164.pdf [firstpage_image] =>[orig_patent_app_number] => 10426687 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426687
Semiconductor integrated circuit having on-chip termination Apr 30, 2003 Issued
Array ( [id] => 1047681 [patent_doc_number] => 06864713 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-08 [patent_title] => 'Multi-stage interconnect architecture for complex programmable logic devices' [patent_app_type] => utility [patent_app_number] => 10/428888 [patent_app_country] => US [patent_app_date] => 2003-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4537 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/864/06864713.pdf [firstpage_image] =>[orig_patent_app_number] => 10428888 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428888
Multi-stage interconnect architecture for complex programmable logic devices Apr 30, 2003 Issued
Array ( [id] => 1031880 [patent_doc_number] => 06879182 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-12 [patent_title] => 'CPLD with multi-function blocks and distributed memory' [patent_app_type] => utility [patent_app_number] => 10/428889 [patent_app_country] => US [patent_app_date] => 2003-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 6184 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/879/06879182.pdf [firstpage_image] =>[orig_patent_app_number] => 10428889 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/428889
CPLD with multi-function blocks and distributed memory Apr 30, 2003 Issued
Array ( [id] => 1172007 [patent_doc_number] => 06756925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'PSK RSFQ output interface' [patent_app_type] => B1 [patent_app_number] => 10/418841 [patent_app_country] => US [patent_app_date] => 2003-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7316 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756925.pdf [firstpage_image] =>[orig_patent_app_number] => 10418841 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/418841
PSK RSFQ output interface Apr 17, 2003 Issued
Array ( [id] => 726742 [patent_doc_number] => 07046176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Rotary encoder' [patent_app_type] => utility [patent_app_number] => 10/497589 [patent_app_country] => US [patent_app_date] => 2003-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3412 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/046/07046176.pdf [firstpage_image] =>[orig_patent_app_number] => 10497589 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/497589
Rotary encoder Apr 10, 2003 Issued
Array ( [id] => 1006548 [patent_doc_number] => 06906653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Digital to analog converter with a weighted capacitive circuit' [patent_app_type] => utility [patent_app_number] => 10/410540 [patent_app_country] => US [patent_app_date] => 2003-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 11981 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906653.pdf [firstpage_image] =>[orig_patent_app_number] => 10410540 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/410540
Digital to analog converter with a weighted capacitive circuit Apr 8, 2003 Issued
Array ( [id] => 1190506 [patent_doc_number] => 06734816 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-11 [patent_title] => 'D/A converter with high jitter resistance' [patent_app_type] => B2 [patent_app_number] => 10/408238 [patent_app_country] => US [patent_app_date] => 2003-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 31 [patent_no_of_words] => 8884 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/734/06734816.pdf [firstpage_image] =>[orig_patent_app_number] => 10408238 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/408238
D/A converter with high jitter resistance Apr 7, 2003 Issued
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