
Lam T. Mai
Examiner (ID: 13914)
| Most Active Art Unit | 2845 |
| Art Unit(s) | 2819, 2845 |
| Total Applications | 2568 |
| Issued Applications | 2446 |
| Pending Applications | 84 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 11803053
[patent_doc_number] => 09543978
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-10
[patent_title] => 'Frequency selective circuit configured to convert an analog input signal to a digital output signal'
[patent_app_type] => utility
[patent_app_number] => 14/769164
[patent_app_country] => US
[patent_app_date] => 2013-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 23
[patent_no_of_words] => 9466
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14769164
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/769164 | Frequency selective circuit configured to convert an analog input signal to a digital output signal | Feb 20, 2013 | Issued |
Array
(
[id] => 9002372
[patent_doc_number] => 20130223497
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-08-29
[patent_title] => 'Method and System for Compensating a Delay Mismatch Between a First Measurement Channel and a Second Measurement Channel'
[patent_app_type] => utility
[patent_app_number] => 13/760198
[patent_app_country] => US
[patent_app_date] => 2013-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1904
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13760198
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/760198 | Method and system for compensating a delay mismatch between a first measurement channel and a second measurement channel | Feb 5, 2013 | Issued |
Array
(
[id] => 9832701
[patent_doc_number] => 08941521
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-01-27
[patent_title] => 'Analog to digital converter and digital to analog converter'
[patent_app_type] => utility
[patent_app_number] => 13/752398
[patent_app_country] => US
[patent_app_date] => 2013-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 11142
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13752398
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/752398 | Analog to digital converter and digital to analog converter | Jan 28, 2013 | Issued |
Array
(
[id] => 9470073
[patent_doc_number] => 08723712
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-05-13
[patent_title] => 'Digital to analog converter with current steering source for reduced glitch energy error'
[patent_app_type] => utility
[patent_app_number] => 13/742532
[patent_app_country] => US
[patent_app_date] => 2013-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 5992
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742532
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/742532 | Digital to analog converter with current steering source for reduced glitch energy error | Jan 15, 2013 | Issued |
Array
(
[id] => 9079653
[patent_doc_number] => 20130265183
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-10-10
[patent_title] => 'NOISE REDUCTION METHOD WITH CHOPPING FOR A MERGED MEMS ACCELEROMETER SENSOR'
[patent_app_type] => utility
[patent_app_number] => 13/742942
[patent_app_country] => US
[patent_app_date] => 2013-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4877
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742942
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/742942 | Noise reduction method with chopping for a merged MEMS accelerometer sensor | Jan 15, 2013 | Issued |
Array
(
[id] => 9504642
[patent_doc_number] => 08742961
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-06-03
[patent_title] => 'Gain and dither capacitor calibration in pipeline analog-to-digital converter stages'
[patent_app_type] => utility
[patent_app_number] => 13/742212
[patent_app_country] => US
[patent_app_date] => 2013-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 6990
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13742212
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/742212 | Gain and dither capacitor calibration in pipeline analog-to-digital converter stages | Jan 14, 2013 | Issued |
Array
(
[id] => 9711975
[patent_doc_number] => 08836555
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-16
[patent_title] => 'Circuit, sensor circuit, and semiconductor device using the sensor circuit'
[patent_app_type] => utility
[patent_app_number] => 13/740801
[patent_app_country] => US
[patent_app_date] => 2013-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 20
[patent_no_of_words] => 12278
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13740801
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/740801 | Circuit, sensor circuit, and semiconductor device using the sensor circuit | Jan 13, 2013 | Issued |
Array
(
[id] => 9484121
[patent_doc_number] => 08730074
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-05-20
[patent_title] => 'Successive approximation analog-to-digital conversion with gain control for tuners'
[patent_app_type] => utility
[patent_app_number] => 13/740472
[patent_app_country] => US
[patent_app_date] => 2013-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3414
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13740472
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/740472 | Successive approximation analog-to-digital conversion with gain control for tuners | Jan 13, 2013 | Issued |
Array
(
[id] => 9497657
[patent_doc_number] => 08736480
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-05-27
[patent_title] => 'Successive approximation analog-to-digital conversion architectural arrangement for receivers'
[patent_app_type] => utility
[patent_app_number] => 13/739510
[patent_app_country] => US
[patent_app_date] => 2013-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 3848
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739510
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/739510 | Successive approximation analog-to-digital conversion architectural arrangement for receivers | Jan 10, 2013 | Issued |
Array
(
[id] => 9484120
[patent_doc_number] => 08730073
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-05-20
[patent_title] => 'Pipelined analog-to-digital converter with dedicated clock cycle for quantization'
[patent_app_type] => utility
[patent_app_number] => 13/738557
[patent_app_country] => US
[patent_app_date] => 2013-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4693
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13738557
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/738557 | Pipelined analog-to-digital converter with dedicated clock cycle for quantization | Jan 9, 2013 | Issued |
Array
(
[id] => 9414495
[patent_doc_number] => 08698534
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-04-15
[patent_title] => 'Digital-to-analog conversion apparatus and current-mode interpolation buffer thereof'
[patent_app_type] => utility
[patent_app_number] => 13/738696
[patent_app_country] => US
[patent_app_date] => 2013-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 9359
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 246
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13738696
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/738696 | Digital-to-analog conversion apparatus and current-mode interpolation buffer thereof | Jan 9, 2013 | Issued |
Array
(
[id] => 11551989
[patent_doc_number] => 09620854
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-04-11
[patent_title] => 'Electronic high frequency device and manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 14/655134
[patent_app_country] => US
[patent_app_date] => 2013-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3659
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14655134
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/655134 | Electronic high frequency device and manufacturing method | Jan 8, 2013 | Issued |
Array
(
[id] => 9402559
[patent_doc_number] => 08692616
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-04-08
[patent_title] => 'Operational amplifier, analog arithmetic circuit, and analog to digital converter'
[patent_app_type] => utility
[patent_app_number] => 13/735056
[patent_app_country] => US
[patent_app_date] => 2013-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 45
[patent_figures_cnt] => 55
[patent_no_of_words] => 31981
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735056
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/735056 | Operational amplifier, analog arithmetic circuit, and analog to digital converter | Jan 6, 2013 | Issued |
Array
(
[id] => 9335959
[patent_doc_number] => 20140062741
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-03-06
[patent_title] => 'SAMPLING CIRCUIT, A/D CONVERTER, D/A CONVERTER, AND CODEC'
[patent_app_type] => utility
[patent_app_number] => 13/882251
[patent_app_country] => US
[patent_app_date] => 2012-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 21142
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13882251
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/882251 | Sampling circuit, A/D converter, D/A converter, and codec | Dec 26, 2012 | Issued |
Array
(
[id] => 8754072
[patent_doc_number] => 20130088376
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-04-11
[patent_title] => 'SIGMA-DELTA MODULATOR WITH SAR ADC AND TRUNCATER AND RELATED SIGMA-DELTA MODULATION METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/691860
[patent_app_country] => US
[patent_app_date] => 2012-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3300
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13691860
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/691860 | Sigma-delta modulator with SAR ADC and truncater and related sigma-delta modulation method | Dec 2, 2012 | Issued |
Array
(
[id] => 9826580
[patent_doc_number] => RE045343
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2015-01-20
[patent_title] => 'Calibration of offset gain and phase errors in M-channel time-interleaved analog-to-digital converters'
[patent_app_type] => reissue
[patent_app_number] => 13/683139
[patent_app_country] => US
[patent_app_date] => 2012-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 35
[patent_no_of_words] => 7119
[patent_no_of_claims] => 52
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 207
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13683139
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/683139 | Calibration of offset gain and phase errors in M-channel time-interleaved analog-to-digital converters | Nov 20, 2012 | Issued |
Array
(
[id] => 10848631
[patent_doc_number] => RE045227
[patent_country] => US
[patent_kind] => E1
[patent_issue_date] => 2014-11-04
[patent_title] => 'Error estimation and correction in a two-channel time-interleaved analog-to-digital converter'
[patent_app_type] => reissue
[patent_app_number] => 13/683118
[patent_app_country] => US
[patent_app_date] => 2012-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 9188
[patent_no_of_claims] => 60
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13683118
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/683118 | Error estimation and correction in a two-channel time-interleaved analog-to-digital converter | Nov 20, 2012 | Issued |
Array
(
[id] => 13272389
[patent_doc_number] => 10148285
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-12-04
[patent_title] => Abstraction and de-abstraction of a digital data stream
[patent_app_type] => utility
[patent_app_number] => 13/677477
[patent_app_country] => US
[patent_app_date] => 2012-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 143
[patent_figures_cnt] => 148
[patent_no_of_words] => 24169
[patent_no_of_claims] => 100
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13677477
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/677477 | Abstraction and de-abstraction of a digital data stream | Nov 14, 2012 | Issued |
Array
(
[id] => 9754668
[patent_doc_number] => 20140285368
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-25
[patent_title] => 'Analog-to-Digital Converter'
[patent_app_type] => utility
[patent_app_number] => 14/355651
[patent_app_country] => US
[patent_app_date] => 2012-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5385
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14355651
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/355651 | Analog-to-digital converter | Oct 28, 2012 | Issued |
Array
(
[id] => 8669480
[patent_doc_number] => 20130044018
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-21
[patent_title] => 'METHOD AND CIRCUIT FOR CONTINUOUS-TIME DELTA-SIGMA DAC WITH REDUCED NOISE'
[patent_app_type] => utility
[patent_app_number] => 13/661114
[patent_app_country] => US
[patent_app_date] => 2012-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4591
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13661114
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/661114 | Method and circuit for continuous-time delta-sigma DAC with reduced noise | Oct 25, 2012 | Issued |