Search

Lam T. Mai

Examiner (ID: 13914)

Most Active Art Unit
2845
Art Unit(s)
2819, 2845
Total Applications
2568
Issued Applications
2446
Pending Applications
84
Abandoned Applications
75

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9142220 [patent_doc_number] => 08582694 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Adaptive digital receiver' [patent_app_type] => utility [patent_app_number] => 13/455071 [patent_app_country] => US [patent_app_date] => 2012-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 10035 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455071 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/455071
Adaptive digital receiver Apr 23, 2012 Issued
Array ( [id] => 9105321 [patent_doc_number] => 20130278452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'SYSTEM AND METHOD OF CLOCKING LOW SAMPLE RATE ANALOG TO DIGITAL CONVERTERS WHILE MINIMIZING LINEARITY ERRORS' [patent_app_type] => utility [patent_app_number] => 13/451774 [patent_app_country] => US [patent_app_date] => 2012-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2560 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13451774 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/451774
System and method of clocking low sample rate analog to digital converters while minimizing linearity errors Apr 19, 2012 Issued
Array ( [id] => 8520473 [patent_doc_number] => 20120319881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'SIGMA-DELTA MODULATOR' [patent_app_type] => utility [patent_app_number] => 13/450866 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7426 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450866 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450866
Sigma-delta modulator having a feed-forward path and a hybrid portion Apr 18, 2012 Issued
Array ( [id] => 8635426 [patent_doc_number] => 20130027229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'METHOD AND APPARATUS FOR SERIALIZING BITS' [patent_app_type] => utility [patent_app_number] => 13/451115 [patent_app_country] => US [patent_app_date] => 2012-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4742 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13451115 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/451115
Method and apparatus for serializing bits Apr 18, 2012 Issued
Array ( [id] => 8921853 [patent_doc_number] => 08487795 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-16 [patent_title] => 'Time-interleaved track-and-hold circuit using distributed global sine-wave clock' [patent_app_type] => utility [patent_app_number] => 13/450204 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 9349 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450204 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450204
Time-interleaved track-and-hold circuit using distributed global sine-wave clock Apr 17, 2012 Issued
Array ( [id] => 8520475 [patent_doc_number] => 20120319883 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-20 [patent_title] => 'TIME-TO-DIGITAL CONVERTER' [patent_app_type] => utility [patent_app_number] => 13/450263 [patent_app_country] => US [patent_app_date] => 2012-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13450263 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/450263
Time-to-digital converter Apr 17, 2012 Issued
Array ( [id] => 9274313 [patent_doc_number] => 08638249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'System and method for high input capacitive signal amplifier' [patent_app_type] => utility [patent_app_number] => 13/447792 [patent_app_country] => US [patent_app_date] => 2012-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 7416 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13447792 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/447792
System and method for high input capacitive signal amplifier Apr 15, 2012 Issued
Array ( [id] => 8995987 [patent_doc_number] => 08519879 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-27 [patent_title] => 'Precision charge-dump circuit' [patent_app_type] => utility [patent_app_number] => 13/446495 [patent_app_country] => US [patent_app_date] => 2012-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6710 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13446495 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/446495
Precision charge-dump circuit Apr 12, 2012 Issued
Array ( [id] => 8983001 [patent_doc_number] => 08514122 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Analog-digital conversion system comprising a double automatic gain control loop' [patent_app_type] => utility [patent_app_number] => 13/446571 [patent_app_country] => US [patent_app_date] => 2012-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5472 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13446571 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/446571
Analog-digital conversion system comprising a double automatic gain control loop Apr 12, 2012 Issued
Array ( [id] => 9027457 [patent_doc_number] => 08537043 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-17 [patent_title] => 'Digital-to-analog converter with controlled gate voltages' [patent_app_type] => utility [patent_app_number] => 13/445183 [patent_app_country] => US [patent_app_date] => 2012-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3577 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13445183 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/445183
Digital-to-analog converter with controlled gate voltages Apr 11, 2012 Issued
Array ( [id] => 9075308 [patent_doc_number] => 08552890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Lossless coding with different parameter selection technique for CABAC in HEVC' [patent_app_type] => utility [patent_app_number] => 13/444710 [patent_app_country] => US [patent_app_date] => 2012-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 15461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13444710 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/444710
Lossless coding with different parameter selection technique for CABAC in HEVC Apr 10, 2012 Issued
Array ( [id] => 8995983 [patent_doc_number] => 08519875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-27 [patent_title] => 'System and method for background calibration of time interleaved analog to digital converters' [patent_app_type] => utility [patent_app_number] => 13/443297 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4923 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443297 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/443297
System and method for background calibration of time interleaved analog to digital converters Apr 9, 2012 Issued
Array ( [id] => 8847150 [patent_doc_number] => 08456337 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-04 [patent_title] => 'System to interface analog-to-digital converters to inputs with arbitrary common-modes' [patent_app_type] => utility [patent_app_number] => 13/442873 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5043 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13442873 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/442873
System to interface analog-to-digital converters to inputs with arbitrary common-modes Apr 9, 2012 Issued
Array ( [id] => 9250850 [patent_doc_number] => 08614634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-24 [patent_title] => '8b/9b encoding for reducing crosstalk on a high speed parallel bus' [patent_app_type] => utility [patent_app_number] => 13/442772 [patent_app_country] => US [patent_app_date] => 2012-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8878 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13442772 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/442772
8b/9b encoding for reducing crosstalk on a high speed parallel bus Apr 8, 2012 Issued
Array ( [id] => 8876768 [patent_doc_number] => 08471736 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-25 [patent_title] => 'Automatic adjusting circuit and method for calibrating vernier time to digital converters' [patent_app_type] => utility [patent_app_number] => 13/441723 [patent_app_country] => US [patent_app_date] => 2012-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13441723 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/441723
Automatic adjusting circuit and method for calibrating vernier time to digital converters Apr 5, 2012 Issued
Array ( [id] => 9100582 [patent_doc_number] => 08564465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Analog to digital conversion apparatus with a reduced number of ADCs' [patent_app_type] => utility [patent_app_number] => 13/440785 [patent_app_country] => US [patent_app_date] => 2012-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2701 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13440785 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/440785
Analog to digital conversion apparatus with a reduced number of ADCs Apr 4, 2012 Issued
Array ( [id] => 8956938 [patent_doc_number] => 08502720 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-06 [patent_title] => 'Parallel digital to analog conversion with image suppression' [patent_app_type] => utility [patent_app_number] => 13/438619 [patent_app_country] => US [patent_app_date] => 2012-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 6411 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13438619 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/438619
Parallel digital to analog conversion with image suppression Apr 2, 2012 Issued
Array ( [id] => 8325327 [patent_doc_number] => 20120197735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'METHOD AND APPARATUS FOR PROVIDING A MOBILE VIDEO BLOG SERVICE' [patent_app_type] => utility [patent_app_number] => 13/437600 [patent_app_country] => US [patent_app_date] => 2012-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4586 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13437600 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/437600
Method and apparatus for providing a mobile video blog service Apr 1, 2012 Issued
Array ( [id] => 9255544 [patent_doc_number] => 08618967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Systems, circuits, and methods for a sigma-delta based time to digital converter' [patent_app_type] => utility [patent_app_number] => 13/435449 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14466 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13435449 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/435449
Systems, circuits, and methods for a sigma-delta based time to digital converter Mar 29, 2012 Issued
Array ( [id] => 8944613 [patent_doc_number] => 08497794 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Analog-digital converter and signal processing system' [patent_app_type] => utility [patent_app_number] => 13/435173 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 36 [patent_no_of_words] => 24383 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13435173 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/435173
Analog-digital converter and signal processing system Mar 29, 2012 Issued
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