
Lam T. Mai
Examiner (ID: 13914)
| Most Active Art Unit | 2845 |
| Art Unit(s) | 2819, 2845 |
| Total Applications | 2568 |
| Issued Applications | 2446 |
| Pending Applications | 84 |
| Abandoned Applications | 75 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6293776
[patent_doc_number] => 20100159855
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-24
[patent_title] => 'TECHNIQUES FOR PRE-DISTORTING TRANSMITTED SIGNALS FOR A TRANSMITTER DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/340518
[patent_app_country] => US
[patent_app_date] => 2008-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4999
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0159/20100159855.pdf
[firstpage_image] =>[orig_patent_app_number] => 12340518
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/340518 | Techniques for pre-distorting transmitted signals for a transmitter device | Dec 18, 2008 | Issued |
Array
(
[id] => 5502448
[patent_doc_number] => 20090163136
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-25
[patent_title] => 'METHOD AND SYSTEM FOR TARIFF, LOAD AND METER DATA MANAGEMENT WITH RADIO RIPPLE CONTROL'
[patent_app_type] => utility
[patent_app_number] => 12/339677
[patent_app_country] => US
[patent_app_date] => 2008-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3364
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0163/20090163136.pdf
[firstpage_image] =>[orig_patent_app_number] => 12339677
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/339677 | Method and system for tariff, load and meter data management with radio ripple control | Dec 18, 2008 | Issued |
Array
(
[id] => 6294298
[patent_doc_number] => 20100159975
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-24
[patent_title] => 'System and Method for Providing a Trunked Radio and Gateway'
[patent_app_type] => utility
[patent_app_number] => 12/340451
[patent_app_country] => US
[patent_app_date] => 2008-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10719
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0159/20100159975.pdf
[firstpage_image] =>[orig_patent_app_number] => 12340451
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/340451 | System and method for providing a trunked radio and gateway | Dec 18, 2008 | Issued |
Array
(
[id] => 73292
[patent_doc_number] => 07755522
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-07-13
[patent_title] => 'Apparatus, method, and circuit for baseline loop analog cancellation'
[patent_app_type] => utility
[patent_app_number] => 12/339002
[patent_app_country] => US
[patent_app_date] => 2008-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 8555
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/755/07755522.pdf
[firstpage_image] =>[orig_patent_app_number] => 12339002
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/339002 | Apparatus, method, and circuit for baseline loop analog cancellation | Dec 17, 2008 | Issued |
Array
(
[id] => 73307
[patent_doc_number] => 07755529
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-13
[patent_title] => 'A/D Converter to convert an analog signal from a bridge circuit to a digital signal'
[patent_app_type] => utility
[patent_app_number] => 12/338875
[patent_app_country] => US
[patent_app_date] => 2008-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 10281
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 231
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/755/07755529.pdf
[firstpage_image] =>[orig_patent_app_number] => 12338875
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/338875 | A/D Converter to convert an analog signal from a bridge circuit to a digital signal | Dec 17, 2008 | Issued |
Array
(
[id] => 65745
[patent_doc_number] => 07760126
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-20
[patent_title] => 'Flash converter differential reference ladder auto-zero circuit'
[patent_app_type] => utility
[patent_app_number] => 12/330272
[patent_app_country] => US
[patent_app_date] => 2008-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2077
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/760/07760126.pdf
[firstpage_image] =>[orig_patent_app_number] => 12330272
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/330272 | Flash converter differential reference ladder auto-zero circuit | Dec 7, 2008 | Issued |
Array
(
[id] => 85162
[patent_doc_number] => 07741987
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-22
[patent_title] => 'Dual gate oxide analog circuit architecture with dual voltage supplies and associated method'
[patent_app_type] => utility
[patent_app_number] => 12/328770
[patent_app_country] => US
[patent_app_date] => 2008-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4625
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/741/07741987.pdf
[firstpage_image] =>[orig_patent_app_number] => 12328770
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/328770 | Dual gate oxide analog circuit architecture with dual voltage supplies and associated method | Dec 4, 2008 | Issued |
Array
(
[id] => 5426473
[patent_doc_number] => 20090085783
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'Multi-Bit Data Converter Using Data Weight Averaging'
[patent_app_type] => utility
[patent_app_number] => 12/328550
[patent_app_country] => US
[patent_app_date] => 2008-12-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7716
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20090085783.pdf
[firstpage_image] =>[orig_patent_app_number] => 12328550
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/328550 | Multi-bit data converter using data weight averaging | Dec 3, 2008 | Issued |
Array
(
[id] => 6241344
[patent_doc_number] => 20100134083
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-06-03
[patent_title] => 'SYSTEM AND METHOD FOR A/D CONVERSION'
[patent_app_type] => utility
[patent_app_number] => 12/326421
[patent_app_country] => US
[patent_app_date] => 2008-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 6150
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0134/20100134083.pdf
[firstpage_image] =>[orig_patent_app_number] => 12326421
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/326421 | System and method for A/D conversion | Dec 1, 2008 | Issued |
Array
(
[id] => 6556628
[patent_doc_number] => 20100127908
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-27
[patent_title] => 'SELF-TIMED CLOCKED ANALOG TO DIGITAL CONVERTER'
[patent_app_type] => utility
[patent_app_number] => 12/324121
[patent_app_country] => US
[patent_app_date] => 2008-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 3543
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20100127908.pdf
[firstpage_image] =>[orig_patent_app_number] => 12324121
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/324121 | Self-timed clocked analog to digital converter | Nov 25, 2008 | Issued |
Array
(
[id] => 6556577
[patent_doc_number] => 20100127904
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-27
[patent_title] => 'IMPLEMENTATION OF A RAPID ARITHMETIC BINARY DECODING SYSTEM OF A SUFFIX LENGTH'
[patent_app_type] => utility
[patent_app_number] => 12/323676
[patent_app_country] => US
[patent_app_date] => 2008-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8173
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0127/20100127904.pdf
[firstpage_image] =>[orig_patent_app_number] => 12323676
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/323676 | IMPLEMENTATION OF A RAPID ARITHMETIC BINARY DECODING SYSTEM OF A SUFFIX LENGTH | Nov 25, 2008 | Abandoned |
Array
(
[id] => 7744901
[patent_doc_number] => 08108002
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-31
[patent_title] => 'Communication apparatuses equipped with more than one subscriber identity card and capable of providing reliable communication quality'
[patent_app_type] => utility
[patent_app_number] => 12/275399
[patent_app_country] => US
[patent_app_date] => 2008-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 6577
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/108/08108002.pdf
[firstpage_image] =>[orig_patent_app_number] => 12275399
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/275399 | Communication apparatuses equipped with more than one subscriber identity card and capable of providing reliable communication quality | Nov 20, 2008 | Issued |
Array
(
[id] => 64081
[patent_doc_number] => 07764208
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-27
[patent_title] => 'Clock dithering process for reducing electromagnetic interference in D/A converters and apparatus for carrying out such process'
[patent_app_type] => utility
[patent_app_number] => 12/275871
[patent_app_country] => US
[patent_app_date] => 2008-11-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 6174
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/764/07764208.pdf
[firstpage_image] =>[orig_patent_app_number] => 12275871
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/275871 | Clock dithering process for reducing electromagnetic interference in D/A converters and apparatus for carrying out such process | Nov 20, 2008 | Issued |
Array
(
[id] => 5320709
[patent_doc_number] => 20090058699
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'Programmable settling for high speed analog to digital converter'
[patent_app_type] => utility
[patent_app_number] => 12/289460
[patent_app_country] => US
[patent_app_date] => 2008-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 8277
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0058/20090058699.pdf
[firstpage_image] =>[orig_patent_app_number] => 12289460
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/289460 | Programmable settling for high speed analog to digital converter | Oct 27, 2008 | Issued |
Array
(
[id] => 5320710
[patent_doc_number] => 20090058700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-03-05
[patent_title] => 'Analog to digital converter with dynamic power configuration'
[patent_app_type] => utility
[patent_app_number] => 12/289310
[patent_app_country] => US
[patent_app_date] => 2008-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7227
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0058/20090058700.pdf
[firstpage_image] =>[orig_patent_app_number] => 12289310
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/289310 | Analog to digital converter with dynamic power configuration | Oct 23, 2008 | Issued |
Array
(
[id] => 7551465
[patent_doc_number] => 08063800
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-11-22
[patent_title] => 'Efficient encoding and decoding of mixed data strings in RFID tags and other media'
[patent_app_type] => utility
[patent_app_number] => 12/740522
[patent_app_country] => US
[patent_app_date] => 2008-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 35
[patent_no_of_words] => 31163
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 218
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/063/08063800.pdf
[firstpage_image] =>[orig_patent_app_number] => 12740522
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/740522 | Efficient encoding and decoding of mixed data strings in RFID tags and other media | Oct 19, 2008 | Issued |
Array
(
[id] => 6581505
[patent_doc_number] => 20100097253
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-22
[patent_title] => 'LOW POWER LINEAR INTERPOLATION DIGITAL-TO-ANALOG CONVERSION'
[patent_app_type] => utility
[patent_app_number] => 12/254441
[patent_app_country] => US
[patent_app_date] => 2008-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 5554
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0097/20100097253.pdf
[firstpage_image] =>[orig_patent_app_number] => 12254441
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/254441 | Low power linear interpolation digital-to-analog conversion | Oct 19, 2008 | Issued |
Array
(
[id] => 65734
[patent_doc_number] => 07760116
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-07-20
[patent_title] => 'Balanced rotator conversion of serialized data'
[patent_app_type] => utility
[patent_app_number] => 12/254010
[patent_app_country] => US
[patent_app_date] => 2008-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3821
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/760/07760116.pdf
[firstpage_image] =>[orig_patent_app_number] => 12254010
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/254010 | Balanced rotator conversion of serialized data | Oct 19, 2008 | Issued |
Array
(
[id] => 5583492
[patent_doc_number] => 20090102694
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-23
[patent_title] => 'High Speed Parallel Procesing Digita Path for SAR ADC'
[patent_app_type] => utility
[patent_app_number] => 12/254678
[patent_app_country] => US
[patent_app_date] => 2008-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4002
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0102/20090102694.pdf
[firstpage_image] =>[orig_patent_app_number] => 12254678
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/254678 | High speed parallel procesing digita path for SAR ADC | Oct 19, 2008 | Issued |
Array
(
[id] => 104526
[patent_doc_number] => 07724166
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-05-25
[patent_title] => 'A/D converter'
[patent_app_type] => utility
[patent_app_number] => 12/253071
[patent_app_country] => US
[patent_app_date] => 2008-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3014
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/724/07724166.pdf
[firstpage_image] =>[orig_patent_app_number] => 12253071
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/253071 | A/D converter | Oct 15, 2008 | Issued |