Search

Lamont B. Koo

Examiner (ID: 647, Phone: (571)272-0984 , Office: P/2823 )

Most Active Art Unit
2813
Art Unit(s)
2823, 2813
Total Applications
628
Issued Applications
465
Pending Applications
72
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10426294 [patent_doc_number] => 20150311305 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'SPIN MOSFET' [patent_app_type] => utility [patent_app_number] => 14/793173 [patent_app_country] => US [patent_app_date] => 2015-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8511 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14793173 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/793173
SPIN MOSFET Jul 6, 2015 Abandoned
Array ( [id] => 11840093 [patent_doc_number] => 20170221814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/329464 [patent_app_country] => US [patent_app_date] => 2015-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13463 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15329464 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/329464
Semiconductor device Jun 30, 2015 Issued
Array ( [id] => 10590763 [patent_doc_number] => 09312386 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Method for forming fin FET structure with dual-stress spacers' [patent_app_type] => utility [patent_app_number] => 14/752940 [patent_app_country] => US [patent_app_date] => 2015-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 4839 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14752940 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/752940
Method for forming fin FET structure with dual-stress spacers Jun 27, 2015 Issued
Array ( [id] => 16067751 [patent_doc_number] => 10692839 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => GaN devices on engineered silicon substrates [patent_app_type] => utility [patent_app_number] => 15/574822 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 7847 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15574822 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/574822
GaN devices on engineered silicon substrates Jun 25, 2015 Issued
Array ( [id] => 11087750 [patent_doc_number] => 20160284718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'Common Source Line with Discrete Contact Plugs' [patent_app_type] => utility [patent_app_number] => 14/734888 [patent_app_country] => US [patent_app_date] => 2015-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14734888 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/734888
Common source line with discrete contact plugs Jun 8, 2015 Issued
Array ( [id] => 10464114 [patent_doc_number] => 20150349129 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'IMAGING ELEMENT, ELECTRONIC APPLIANCE, METHOD FOR DRIVING IMAGING DEVICE, AND METHOD FOR DRIVING ELECTRONIC APPLIANCE' [patent_app_type] => utility [patent_app_number] => 14/721023 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 16273 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721023 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/721023
Imaging element, electronic appliance, method for driving imaging device, and method for driving electronic appliance May 25, 2015 Issued
Array ( [id] => 11315565 [patent_doc_number] => 20160351675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING REPLACEMENT METAL GATE ELECTRODES' [patent_app_type] => utility [patent_app_number] => 14/721822 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7677 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721822 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/721822
INTEGRATED CIRCUITS AND METHODS FOR FABRICATING INTEGRATED CIRCUITS HAVING REPLACEMENT METAL GATE ELECTRODES May 25, 2015 Abandoned
Array ( [id] => 10464278 [patent_doc_number] => 20150349293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'ORGANIC LIGHT EMITTING DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/721698 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6949 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721698 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/721698
Organic light emitting display panel and method of manufacturing the same May 25, 2015 Issued
Array ( [id] => 11315343 [patent_doc_number] => 20160351453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-01 [patent_title] => 'METHOD AND STRUCTURE FOR FORMATION OF REPLACEMENT METAL GATE FIELD EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/721402 [patent_app_country] => US [patent_app_date] => 2015-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5077 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14721402 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/721402
Method and structure for formation of replacement metal gate field effect transistors May 25, 2015 Issued
Array ( [id] => 15315601 [patent_doc_number] => 10522517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-31 [patent_title] => Half-bridge power semiconductor module and manufacturing method therefor [patent_app_type] => utility [patent_app_number] => 15/322765 [patent_app_country] => US [patent_app_date] => 2015-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 21 [patent_no_of_words] => 13034 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 324 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15322765 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/322765
Half-bridge power semiconductor module and manufacturing method therefor May 24, 2015 Issued
Array ( [id] => 15139551 [patent_doc_number] => 10483262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Dual nitride stressor for semiconductor device and method of manufacturing [patent_app_type] => utility [patent_app_number] => 14/714229 [patent_app_country] => US [patent_app_date] => 2015-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 4992 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14714229 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/714229
Dual nitride stressor for semiconductor device and method of manufacturing May 14, 2015 Issued
Array ( [id] => 10507002 [patent_doc_number] => 09234872 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Chemical sensing and/or measuring devices and methods' [patent_app_type] => utility [patent_app_number] => 14/673700 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4602 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14673700 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/673700
Chemical sensing and/or measuring devices and methods Mar 29, 2015 Issued
Array ( [id] => 14430089 [patent_doc_number] => 10319860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Overlap capacitance nanowire [patent_app_type] => utility [patent_app_number] => 14/667349 [patent_app_country] => US [patent_app_date] => 2015-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 33 [patent_no_of_words] => 4384 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14667349 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/667349
Overlap capacitance nanowire Mar 23, 2015 Issued
Array ( [id] => 11071481 [patent_doc_number] => 20160268446 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-15 [patent_title] => 'TRENCH VERTICAL JFET WITH IMPROVED THRESHOLD VOLTAGE CONTROL' [patent_app_type] => utility [patent_app_number] => 14/642936 [patent_app_country] => US [patent_app_date] => 2015-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3587 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14642936 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/642936
TRENCH VERTICAL JFET WITH IMPROVED THRESHOLD VOLTAGE CONTROL Mar 9, 2015 Abandoned
Array ( [id] => 12215025 [patent_doc_number] => 09911843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-06 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/636149 [patent_app_country] => US [patent_app_date] => 2015-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 32 [patent_no_of_words] => 11800 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14636149 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/636149
Semiconductor device Mar 1, 2015 Issued
Array ( [id] => 12936289 [patent_doc_number] => 09831328 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-28 [patent_title] => Bipolar junction transistor (BJT) base conductor pullback [patent_app_type] => utility [patent_app_number] => 14/620326 [patent_app_country] => US [patent_app_date] => 2015-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 6226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14620326 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/620326
Bipolar junction transistor (BJT) base conductor pullback Feb 11, 2015 Issued
Array ( [id] => 10315272 [patent_doc_number] => 20150200275 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-16 [patent_title] => 'FINFET AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/585053 [patent_app_country] => US [patent_app_date] => 2014-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14585053 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/585053
FINFET AND METHOD FOR MANUFACTURING THE SAME Dec 28, 2014 Abandoned
Array ( [id] => 10217427 [patent_doc_number] => 20150102420 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/576158 [patent_app_country] => US [patent_app_date] => 2014-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6230 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576158 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576158
Semiconductor device comprising a plurality of cell arrays including a well potential supply region and adjacent dummy gates provided on a well region of a cell array Dec 17, 2014 Issued
Array ( [id] => 10302821 [patent_doc_number] => 20150187821 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'THIN FILM TRANSISTOR ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/572521 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4240 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14572521 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/572521
Thin film transistor array substrate and method for manufacturing the same Dec 15, 2014 Issued
Array ( [id] => 10826211 [patent_doc_number] => 20160172379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'MODIFIED FIN CUT AFTER EPITAXIAL GROWTH' [patent_app_type] => utility [patent_app_number] => 14/571504 [patent_app_country] => US [patent_app_date] => 2014-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 5842 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14571504 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/571504
Modified fin cut after epitaxial growth Dec 15, 2014 Issued
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