Search

Lamont B. Koo

Examiner (ID: 647, Phone: (571)272-0984 , Office: P/2823 )

Most Active Art Unit
2813
Art Unit(s)
2823, 2813
Total Applications
628
Issued Applications
465
Pending Applications
72
Abandoned Applications
107

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9094411 [patent_doc_number] => 20130273722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-17 [patent_title] => 'CONTACT ON A HETEROGENEOUS SEMICONDUCTOR SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 13/860845 [patent_app_country] => US [patent_app_date] => 2013-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3866 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13860845 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/860845
Contact on a heterogeneous semiconductor substrate Apr 10, 2013 Issued
Array ( [id] => 9107759 [patent_doc_number] => 20130280891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'METHOD AND APPARATUS FOR GERMANIUM TIN ALLOY FORMATION BY THERMAL CVD' [patent_app_type] => utility [patent_app_number] => 13/784109 [patent_app_country] => US [patent_app_date] => 2013-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5895 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13784109 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/784109
METHOD AND APPARATUS FOR GERMANIUM TIN ALLOY FORMATION BY THERMAL CVD Mar 28, 2013 Abandoned
Array ( [id] => 9421877 [patent_doc_number] => 20140106528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS' [patent_app_type] => utility [patent_app_number] => 13/793662 [patent_app_country] => US [patent_app_date] => 2013-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4842 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13793662 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/793662
FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS Mar 10, 2013 Abandoned
Array ( [id] => 9716858 [patent_doc_number] => 20140252556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES' [patent_app_type] => utility [patent_app_number] => 13/786520 [patent_app_country] => US [patent_app_date] => 2013-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2215 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13786520 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/786520
SINGLE-MASK SPACER TECHNIQUE FOR SEMICONDUCTOR DEVICE FEATURES Mar 5, 2013 Abandoned
Array ( [id] => 9145248 [patent_doc_number] => 20130299771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'Semiconductor Device Including Transistor' [patent_app_type] => utility [patent_app_number] => 13/748622 [patent_app_country] => US [patent_app_date] => 2013-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10895 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748622 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748622
Semiconductor Device Including Transistor Jan 23, 2013 Abandoned
Array ( [id] => 8866105 [patent_doc_number] => 20130149808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'METHOD OF FABRICATING A SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 13/743920 [patent_app_country] => US [patent_app_date] => 2013-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8912 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13743920 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/743920
METHOD OF FABRICATING A SOLAR CELL Jan 16, 2013 Abandoned
Array ( [id] => 9600688 [patent_doc_number] => 20140197370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-17 [patent_title] => 'OVERLAP CAPACITANCE NANOWIRE' [patent_app_type] => utility [patent_app_number] => 13/739182 [patent_app_country] => US [patent_app_date] => 2013-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4582 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13739182 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/739182
Overlap capacitance nanowire Jan 10, 2013 Issued
Array ( [id] => 12396657 [patent_doc_number] => 09966477 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Charge trapping split gate device and method of fabricating same [patent_app_type] => utility [patent_app_number] => 13/715185 [patent_app_country] => US [patent_app_date] => 2012-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5016 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13715185 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/715185
Charge trapping split gate device and method of fabricating same Dec 13, 2012 Issued
Array ( [id] => 11201066 [patent_doc_number] => 09431287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Chemical mechanical planarization process and structures' [patent_app_type] => utility [patent_app_number] => 13/714016 [patent_app_country] => US [patent_app_date] => 2012-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1900 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 371 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13714016 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/714016
Chemical mechanical planarization process and structures Dec 12, 2012 Issued
Array ( [id] => 11740260 [patent_doc_number] => 09704853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-11 [patent_title] => 'Semiconductor device and driver circuit with an active device and isolation structure interconnected through a resistor circuit, and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 13/671506 [patent_app_country] => US [patent_app_date] => 2012-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 21 [patent_no_of_words] => 17291 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13671506 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/671506
Semiconductor device and driver circuit with an active device and isolation structure interconnected through a resistor circuit, and method of manufacture thereof Nov 6, 2012 Issued
Array ( [id] => 8987008 [patent_doc_number] => 20130214289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'Short-Resistant Metal-Gate MOS Transistor and Method of Forming the Transistor' [patent_app_type] => utility [patent_app_number] => 13/658785 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 7568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658785 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658785
Short-Resistant Metal-Gate MOS Transistor and Method of Forming the Transistor Oct 22, 2012 Abandoned
Array ( [id] => 9432860 [patent_doc_number] => 20140110766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/657026 [patent_app_country] => US [patent_app_date] => 2012-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2937 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13657026 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/657026
Semiconductor structure and manufacturing method of forming a large pattern and a plurality of fine gate lines located between the large patterns Oct 21, 2012 Issued
Array ( [id] => 9432858 [patent_doc_number] => 20140110764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'Method to control amorphous oxide layer formation at interfaces of thin film stacks for memory and logic components' [patent_app_type] => utility [patent_app_number] => 13/655838 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9816 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655838 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/655838
Method to control amorphous oxide layer formation at interfaces of thin film stacks for memory and logic components Oct 18, 2012 Abandoned
Array ( [id] => 9259758 [patent_doc_number] => 20130341687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'METAL SILICIDE LAYER, NMOS TRANSISTOR, AND FABRICATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/654518 [patent_app_country] => US [patent_app_date] => 2012-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4486 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654518 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654518
Metal silicide layer, NMOS transistor, and fabrication method Oct 17, 2012 Issued
Array ( [id] => 9418801 [patent_doc_number] => 20140103451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS' [patent_app_type] => utility [patent_app_number] => 13/654010 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4806 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13654010 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/654010
FINFET CIRCUITS WITH VARIOUS FIN HEIGHTS Oct 16, 2012 Abandoned
Array ( [id] => 9418754 [patent_doc_number] => 20140103404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'REPLACEMENT GATE WITH AN INNER DIELECTRIC SPACER' [patent_app_type] => utility [patent_app_number] => 13/653658 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653658 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653658
REPLACEMENT GATE WITH AN INNER DIELECTRIC SPACER Oct 16, 2012 Abandoned
Array ( [id] => 10060194 [patent_doc_number] => 09099558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Fin FET structure with dual-stress spacers and method for forming the same' [patent_app_type] => utility [patent_app_number] => 13/653329 [patent_app_country] => US [patent_app_date] => 2012-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 28 [patent_no_of_words] => 4838 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653329 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653329
Fin FET structure with dual-stress spacers and method for forming the same Oct 15, 2012 Issued
Array ( [id] => 9418800 [patent_doc_number] => 20140103450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'HYBRID ORIENTATION FIN FIELD EFFECT TRANSISTOR AND PLANAR FIELD EFFECT TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 13/650591 [patent_app_country] => US [patent_app_date] => 2012-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8917 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13650591 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/650591
Hybrid orientation fin field effect transistor and planar field effect transistor Oct 11, 2012 Issued
Array ( [id] => 9316544 [patent_doc_number] => 20140048882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-20 [patent_title] => 'TECHNIQUES FOR GATE WORKFUNCTION ENGINEERING TO REDUCE SHORT CHANNEL EFFECTS IN PLANAR CMOS DEVICES' [patent_app_type] => utility [patent_app_number] => 13/617283 [patent_app_country] => US [patent_app_date] => 2012-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4065 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13617283 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/617283
Techniques for gate workfunction engineering to reduce short channel effects in planar CMOS devices Sep 13, 2012 Issued
Array ( [id] => 9335014 [patent_doc_number] => 20140061796 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'TECHNIQUES FOR METAL GATE WORKFUNCTION ENGINEERING TO ENABLE MULTIPLE THRESHOLD VOLTAGE FINFET DEVICES' [patent_app_type] => utility [patent_app_number] => 13/611257 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5094 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611257 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/611257
Techniques for metal gate workfunction engineering to enable multiple threshold voltage FINFET devices Sep 11, 2012 Issued
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