Search

Lan Vinh

Examiner (ID: 2362, Phone: (571)272-1471 , Office: P/1713 )

Most Active Art Unit
1713
Art Unit(s)
1765, 1792, 1713
Total Applications
1662
Issued Applications
1401
Pending Applications
46
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7287352 [patent_doc_number] => 20040147127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Fabrication method of semiconductor integrated circuit device' [patent_app_type] => new [patent_app_number] => 10/742932 [patent_app_country] => US [patent_app_date] => 2003-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 80 [patent_figures_cnt] => 80 [patent_no_of_words] => 31931 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147127.pdf [firstpage_image] =>[orig_patent_app_number] => 10742932 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/742932
Fabrication method of semiconductor integrated circuit device Dec 22, 2003 Issued
Array ( [id] => 847176 [patent_doc_number] => 07384876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-06-10 [patent_title] => 'Method and apparatus for determining consumable lifetime' [patent_app_type] => utility [patent_app_number] => 10/539705 [patent_app_country] => US [patent_app_date] => 2003-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4376 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/384/07384876.pdf [firstpage_image] =>[orig_patent_app_number] => 10539705 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/539705
Method and apparatus for determining consumable lifetime Dec 18, 2003 Issued
Array ( [id] => 5724977 [patent_doc_number] => 20060055737 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Ink jet printhead and relative manufacturing process' [patent_app_type] => utility [patent_app_number] => 10/538743 [patent_app_country] => US [patent_app_date] => 2003-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4668 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20060055737.pdf [firstpage_image] =>[orig_patent_app_number] => 10538743 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/538743
Ink jet printhead and relative manufacturing process Dec 15, 2003 Issued
Array ( [id] => 7462787 [patent_doc_number] => 20040198059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Method of forming metal line of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/735228 [patent_app_country] => US [patent_app_date] => 2003-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2190 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20040198059.pdf [firstpage_image] =>[orig_patent_app_number] => 10735228 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/735228
Method of forming metal line of semiconductor device Dec 11, 2003 Issued
Array ( [id] => 6939335 [patent_doc_number] => 20050112898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Method for etching a substrate and a device formed using the method' [patent_app_type] => utility [patent_app_number] => 10/721932 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3406 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20050112898.pdf [firstpage_image] =>[orig_patent_app_number] => 10721932 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/721932
Method for etching a substrate and a device formed using the method Nov 24, 2003 Issued
Array ( [id] => 184590 [patent_doc_number] => 07645356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Method of processing wafers with resonant heating' [patent_app_type] => utility [patent_app_number] => 10/721657 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 1939 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/645/07645356.pdf [firstpage_image] =>[orig_patent_app_number] => 10721657 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/721657
Method of processing wafers with resonant heating Nov 24, 2003 Issued
Array ( [id] => 510024 [patent_doc_number] => 07196017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Method for etching smooth sidewalls in III-V based compounds for electro-optical devices' [patent_app_type] => utility [patent_app_number] => 10/692772 [patent_app_country] => US [patent_app_date] => 2003-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1545 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196017.pdf [firstpage_image] =>[orig_patent_app_number] => 10692772 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/692772
Method for etching smooth sidewalls in III-V based compounds for electro-optical devices Oct 23, 2003 Issued
Array ( [id] => 515236 [patent_doc_number] => 07192886 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Method for using additives in the caustic etching of silicon for obtaining improved surface characteristics' [patent_app_type] => utility [patent_app_number] => 10/692661 [patent_app_country] => US [patent_app_date] => 2003-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3261 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/192/07192886.pdf [firstpage_image] =>[orig_patent_app_number] => 10692661 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/692661
Method for using additives in the caustic etching of silicon for obtaining improved surface characteristics Oct 23, 2003 Issued
Array ( [id] => 741087 [patent_doc_number] => 07030017 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method for the planarization of a semiconductor structure' [patent_app_type] => utility [patent_app_number] => 10/692234 [patent_app_country] => US [patent_app_date] => 2003-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2281 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030017.pdf [firstpage_image] =>[orig_patent_app_number] => 10692234 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/692234
Method for the planarization of a semiconductor structure Oct 22, 2003 Issued
Array ( [id] => 6991072 [patent_doc_number] => 20050090109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'CMP method for copper, tungsten, titanium, polysilicon, and other substrates using organosulfonic acids as oxidizers' [patent_app_type] => utility [patent_app_number] => 10/690623 [patent_app_country] => US [patent_app_date] => 2003-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9816 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20050090109.pdf [firstpage_image] =>[orig_patent_app_number] => 10690623 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/690623
CMP method for copper, tungsten, titanium, polysilicon, and other substrates using organosulfonic acids as oxidizers Oct 22, 2003 Issued
Array ( [id] => 7317829 [patent_doc_number] => 20040134615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Device and method for anisotropic plasma etching of a substrate, particularly a silicon element' [patent_app_type] => new [patent_app_number] => 10/691108 [patent_app_country] => US [patent_app_date] => 2003-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10176 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20040134615.pdf [firstpage_image] =>[orig_patent_app_number] => 10691108 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/691108
Device and method for anisotropic plasma etching of a substrate, particularly a silicon element Oct 21, 2003 Issued
Array ( [id] => 7383571 [patent_doc_number] => 20040082182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Method of making metallization and contact structures in an integrated circuit using a timed trench etch' [patent_app_type] => new [patent_app_number] => 10/689034 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6871 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082182.pdf [firstpage_image] =>[orig_patent_app_number] => 10689034 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/689034
Method of making metallization and contact structures in an integrated circuit using a timed trench etch Oct 20, 2003 Abandoned
Array ( [id] => 741134 [patent_doc_number] => 07030030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and mask-pattern generation method' [patent_app_type] => utility [patent_app_number] => 10/688902 [patent_app_country] => US [patent_app_date] => 2003-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 48 [patent_no_of_words] => 16174 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/030/07030030.pdf [firstpage_image] =>[orig_patent_app_number] => 10688902 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/688902
Method of manufacturing a semiconductor integrated circuit device having a plurality of wiring layers and mask-pattern generation method Oct 20, 2003 Issued
Array ( [id] => 899972 [patent_doc_number] => 07338908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-03-04 [patent_title] => 'Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage' [patent_app_type] => utility [patent_app_number] => 10/690084 [patent_app_country] => US [patent_app_date] => 2003-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6854 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/338/07338908.pdf [firstpage_image] =>[orig_patent_app_number] => 10690084 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/690084
Method for fabrication of semiconductor interconnect structure with reduced capacitance, leakage current, and improved breakdown voltage Oct 19, 2003 Issued
Array ( [id] => 425121 [patent_doc_number] => 07271103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-18 [patent_title] => 'Surface treated low-k dielectric as diffusion barrier for copper metallization' [patent_app_type] => utility [patent_app_number] => 10/687713 [patent_app_country] => US [patent_app_date] => 2003-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2172 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/271/07271103.pdf [firstpage_image] =>[orig_patent_app_number] => 10687713 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/687713
Surface treated low-k dielectric as diffusion barrier for copper metallization Oct 16, 2003 Issued
Array ( [id] => 925682 [patent_doc_number] => 07316980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-08 [patent_title] => 'Method for forming ferrocapacitors and FeRAM devices' [patent_app_type] => utility [patent_app_number] => 10/678758 [patent_app_country] => US [patent_app_date] => 2003-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 1396 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/316/07316980.pdf [firstpage_image] =>[orig_patent_app_number] => 10678758 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/678758
Method for forming ferrocapacitors and FeRAM devices Oct 1, 2003 Issued
Array ( [id] => 7280944 [patent_doc_number] => 20040063321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-01 [patent_title] => 'Method for fabricating a semiconductor configuration' [patent_app_type] => new [patent_app_number] => 10/675766 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3769 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20040063321.pdf [firstpage_image] =>[orig_patent_app_number] => 10675766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/675766
Method for fabricating a semiconductor configuration Sep 29, 2003 Abandoned
Array ( [id] => 7304627 [patent_doc_number] => 20040140287 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-22 [patent_title] => 'Edge and bevel cleaning process and system' [patent_app_type] => new [patent_app_number] => 10/676895 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4482 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0140/20040140287.pdf [firstpage_image] =>[orig_patent_app_number] => 10676895 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/676895
Edge and bevel cleaning process and system Sep 29, 2003 Abandoned
Array ( [id] => 715628 [patent_doc_number] => 07053001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Selective etching processes for In2O3 thin films in FeRAM device applications' [patent_app_type] => utility [patent_app_number] => 10/676983 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 1861 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/053/07053001.pdf [firstpage_image] =>[orig_patent_app_number] => 10676983 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/676983
Selective etching processes for In2O3 thin films in FeRAM device applications Sep 29, 2003 Issued
Array ( [id] => 650958 [patent_doc_number] => 07112535 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-26 [patent_title] => 'Precision polysilicon resistor process' [patent_app_type] => utility [patent_app_number] => 10/605439 [patent_app_country] => US [patent_app_date] => 2003-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4076 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/112/07112535.pdf [firstpage_image] =>[orig_patent_app_number] => 10605439 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605439
Precision polysilicon resistor process Sep 29, 2003 Issued
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