Search

Lan Vinh

Examiner (ID: 2362, Phone: (571)272-1471 , Office: P/1713 )

Most Active Art Unit
1713
Art Unit(s)
1765, 1792, 1713
Total Applications
1662
Issued Applications
1401
Pending Applications
46
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7439751 [patent_doc_number] => 20040050496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Plasma processing apparatus and plasma processing method' [patent_app_type] => new [patent_app_number] => 10/621497 [patent_app_country] => US [patent_app_date] => 2003-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6745 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0050/20040050496.pdf [firstpage_image] =>[orig_patent_app_number] => 10621497 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/621497
Plasma processing apparatus and plasma processing method Jul 16, 2003 Issued
Array ( [id] => 7122549 [patent_doc_number] => 20050014378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Substrate patterning integration' [patent_app_type] => utility [patent_app_number] => 10/621744 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2114 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20050014378.pdf [firstpage_image] =>[orig_patent_app_number] => 10621744 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/621744
Substrate patterning integration Jul 15, 2003 Abandoned
Array ( [id] => 515155 [patent_doc_number] => 07192874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Method for reducing foreign material concentrations in etch chambers' [patent_app_type] => utility [patent_app_number] => 10/604367 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3439 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/192/07192874.pdf [firstpage_image] =>[orig_patent_app_number] => 10604367 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604367
Method for reducing foreign material concentrations in etch chambers Jul 14, 2003 Issued
Array ( [id] => 7360026 [patent_doc_number] => 20040014318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Slurry for use with fixed-abrasive polishing pads in polishing semiconductor device conductive structures that include copper and tungsten' [patent_app_type] => new [patent_app_number] => 10/620002 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4756 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20040014318.pdf [firstpage_image] =>[orig_patent_app_number] => 10620002 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/620002
Slurry for use with fixed-abrasive polishing pads in polishing semiconductor device conductive structures that include copper and tungsten Jul 13, 2003 Abandoned
Array ( [id] => 715624 [patent_doc_number] => 07052999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/617226 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3024 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/052/07052999.pdf [firstpage_image] =>[orig_patent_app_number] => 10617226 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/617226
Method for fabricating semiconductor device Jul 10, 2003 Issued
Array ( [id] => 7089230 [patent_doc_number] => 20050009343 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/619052 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3537 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20050009343.pdf [firstpage_image] =>[orig_patent_app_number] => 10619052 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/619052
Method and structure for a self-aligned silicided word line and polysilicon plug during the formation of a semiconductor device Jul 9, 2003 Issued
Array ( [id] => 7675084 [patent_doc_number] => 20040127034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/608530 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1963 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20040127034.pdf [firstpage_image] =>[orig_patent_app_number] => 10608530 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608530
Method for fabricating semiconductor device Jun 29, 2003 Issued
Array ( [id] => 7360052 [patent_doc_number] => 20040014321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Methods for manufacturing contact plugs for semiconductor devices' [patent_app_type] => new [patent_app_number] => 10/609505 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2565 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20040014321.pdf [firstpage_image] =>[orig_patent_app_number] => 10609505 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609505
Methods for manufacturing contact plugs for semiconductor devices Jun 29, 2003 Abandoned
Array ( [id] => 7430187 [patent_doc_number] => 20040266195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'METHODS OF PLANARIZATION' [patent_app_type] => new [patent_app_number] => 10/604196 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1972 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266195.pdf [firstpage_image] =>[orig_patent_app_number] => 10604196 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604196
Methods of planarization Jun 29, 2003 Issued
Array ( [id] => 7675064 [patent_doc_number] => 20040127054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Method for manufacturing magnetic random access memory' [patent_app_type] => new [patent_app_number] => 10/608081 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1745 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20040127054.pdf [firstpage_image] =>[orig_patent_app_number] => 10608081 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608081
Method for manufacturing magnetic random access memory Jun 29, 2003 Abandoned
Array ( [id] => 7430080 [patent_doc_number] => 20040266184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Post-deposition modification of interlayer dielectrics' [patent_app_type] => new [patent_app_number] => 10/609963 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5279 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266184.pdf [firstpage_image] =>[orig_patent_app_number] => 10609963 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609963
Post-deposition modification of interlayer dielectrics Jun 29, 2003 Abandoned
Array ( [id] => 724523 [patent_doc_number] => 07045467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Method for determining endpoint of etch layer and etching process implementing said method in semiconductor element fabrication' [patent_app_type] => utility [patent_app_number] => 10/607942 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3895 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045467.pdf [firstpage_image] =>[orig_patent_app_number] => 10607942 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/607942
Method for determining endpoint of etch layer and etching process implementing said method in semiconductor element fabrication Jun 26, 2003 Issued
Array ( [id] => 7365342 [patent_doc_number] => 20040092113 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Process for forming a dual damascene structure' [patent_app_type] => new [patent_app_number] => 10/608286 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1718 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092113.pdf [firstpage_image] =>[orig_patent_app_number] => 10608286 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608286
Process for forming a dual damascene structure Jun 26, 2003 Issued
Array ( [id] => 510027 [patent_doc_number] => 07196018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Semiconductor etching paste and the use thereof for localized etching of semiconductor substrates' [patent_app_type] => utility [patent_app_number] => 10/609015 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 5 [patent_no_of_words] => 6086 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/196/07196018.pdf [firstpage_image] =>[orig_patent_app_number] => 10609015 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/609015
Semiconductor etching paste and the use thereof for localized etching of semiconductor substrates Jun 26, 2003 Issued
Array ( [id] => 376753 [patent_doc_number] => 07311851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Apparatus and method for reactive atom plasma processing for material deposition' [patent_app_type] => utility [patent_app_number] => 10/608384 [patent_app_country] => US [patent_app_date] => 2003-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7597 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/311/07311851.pdf [firstpage_image] =>[orig_patent_app_number] => 10608384 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608384
Apparatus and method for reactive atom plasma processing for material deposition Jun 26, 2003 Issued
Array ( [id] => 7412384 [patent_doc_number] => 20040263827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Novel methodology for in-situ and real-time chamber condition monitoring and process recovery during plasma processing' [patent_app_type] => new [patent_app_number] => 10/608670 [patent_app_country] => US [patent_app_date] => 2003-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3350 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0263/20040263827.pdf [firstpage_image] =>[orig_patent_app_number] => 10608670 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/608670
Methodology for in-situ and real-time chamber condition monitoring and process recovery during plasma processing Jun 25, 2003 Issued
Array ( [id] => 7430250 [patent_doc_number] => 20040266202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'MULTI-RUN SELECTIVE PATTERN AND ETCH WAFER PROCESS' [patent_app_type] => new [patent_app_number] => 10/604087 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5725 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266202.pdf [firstpage_image] =>[orig_patent_app_number] => 10604087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/604087
Multi-run selective pattern and etch wafer process Jun 24, 2003 Issued
Array ( [id] => 6909911 [patent_doc_number] => 20050173669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Polishing fluid and method of polishing' [patent_app_type] => utility [patent_app_number] => 10/517049 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9027 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20050173669.pdf [firstpage_image] =>[orig_patent_app_number] => 10517049 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/517049
Polishing fluid and method of polishing May 28, 2003 Issued
Array ( [id] => 6804779 [patent_doc_number] => 20030232173 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-18 [patent_title] => 'Method for manufacturing glass substrate' [patent_app_type] => new [patent_app_number] => 10/447750 [patent_app_country] => US [patent_app_date] => 2003-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6411 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20030232173.pdf [firstpage_image] =>[orig_patent_app_number] => 10447750 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/447750
Method for manufacturing glass substrate May 28, 2003 Issued
Array ( [id] => 682541 [patent_doc_number] => 07081414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Deposition-selective etch-deposition process for dielectric film gapfill' [patent_app_type] => utility [patent_app_number] => 10/445240 [patent_app_country] => US [patent_app_date] => 2003-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9484 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/081/07081414.pdf [firstpage_image] =>[orig_patent_app_number] => 10445240 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/445240
Deposition-selective etch-deposition process for dielectric film gapfill May 22, 2003 Issued
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