
Lan Vinh
Examiner (ID: 2362, Phone: (571)272-1471 , Office: P/1713 )
| Most Active Art Unit | 1713 |
| Art Unit(s) | 1765, 1792, 1713 |
| Total Applications | 1662 |
| Issued Applications | 1401 |
| Pending Applications | 46 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7365827
[patent_doc_number] => 20040005787
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-08
[patent_title] => 'Method to reduce residual particulate contamination in CVD and PVD semiconductor wafer manufacturing'
[patent_app_type] => new
[patent_app_number] => 10/188490
[patent_app_country] => US
[patent_app_date] => 2002-07-02
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0005/20040005787.pdf
[firstpage_image] =>[orig_patent_app_number] => 10188490
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/188490 | Method to reduce residual particulate contamination in CVD and PVD semiconductor wafer manufacturing | Jul 1, 2002 | Issued |
Array
(
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[patent_doc_number] => 20040004056
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[patent_issue_date] => 2004-01-08
[patent_title] => 'Method of etching a film of magnetic material and method of manufacturing a thin-film magnetic head'
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[patent_app_number] => 10/186428
[patent_app_country] => US
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Array
(
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[patent_issue_date] => 2004-09-07
[patent_title] => 'Method of manufacturing a semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/184898 | Method of manufacturing a semiconductor device | Jun 30, 2002 | Issued |
Array
(
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[patent_kind] => B2
[patent_issue_date] => 2006-11-28
[patent_title] => 'Method for evaluating dependence of properties of semiconductor substrate on plane orientation and semiconductor device using the same'
[patent_app_type] => utility
[patent_app_number] => 10/175076
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/175076 | Method for evaluating dependence of properties of semiconductor substrate on plane orientation and semiconductor device using the same | Jun 19, 2002 | Issued |
Array
(
[id] => 1071501
[patent_doc_number] => 06841082
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[patent_issue_date] => 2005-01-11
[patent_title] => 'Method of manufacturing Er-doped silicon nano-dot array and laser ablation appparatus used therein'
[patent_app_type] => utility
[patent_app_number] => 10/171751
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/171751 | Method of manufacturing Er-doped silicon nano-dot array and laser ablation appparatus used therein | Jun 11, 2002 | Issued |
Array
(
[id] => 7344359
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[patent_title] => 'Dry-etcching method'
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[firstpage_image] =>[orig_patent_app_number] => 10480821
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/480821 | Dry-etching method | Jun 6, 2002 | Issued |
Array
(
[id] => 6838938
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[patent_title] => 'Method for fabricating a gate stack in very large scale integrated semiconductor memories'
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[patent_app_number] => 10/159155
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[pdf_file] => publications/A1/0036/20030036278.pdf
[firstpage_image] =>[orig_patent_app_number] => 10159155
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/159155 | Method for fabricating a gate stack in very large scale integrated semiconductor memories | May 30, 2002 | Issued |
Array
(
[id] => 1119891
[patent_doc_number] => 06797636
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-09-28
[patent_title] => 'Process of fabricating DRAM cells with collar isolation layers'
[patent_app_type] => B2
[patent_app_number] => 10/157870
[patent_app_country] => US
[patent_app_date] => 2002-05-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/157870 | Process of fabricating DRAM cells with collar isolation layers | May 30, 2002 | Issued |
Array
(
[id] => 1059551
[patent_doc_number] => 06852641
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-08
[patent_title] => 'Method of spiking mixed acid liquid in reactor'
[patent_app_type] => utility
[patent_app_number] => 10/063975
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 10063975
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/063975 | Method of spiking mixed acid liquid in reactor | May 29, 2002 | Issued |
Array
(
[id] => 1126743
[patent_doc_number] => 06790782
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[patent_issue_date] => 2004-09-14
[patent_title] => 'Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal'
[patent_app_type] => B1
[patent_app_number] => 10/157450
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[firstpage_image] =>[orig_patent_app_number] => 10157450
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/157450 | Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal | May 28, 2002 | Issued |
Array
(
[id] => 6260713
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[patent_title] => 'Polishing method using ceria slurry, and method of manufacturing semiconductor device'
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Array
(
[id] => 6701703
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[patent_title] => 'Method for plasma etching a wafer after backside grinding'
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Array
(
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Array
(
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[patent_title] => 'Fabrication process for bonded wafer precision layer thickness control and its non-destructructive measurement method'
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Array
(
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[patent_title] => 'Method and apparatuses for making and using bi-modal abrasive slurries for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies'
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Array
(
[id] => 6425482
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Array
(
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/142496 | Method of forming silicidation blocking layer | May 9, 2002 | Issued |
Array
(
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[patent_title] => 'Thin-film-transistor-array substrate, thin-film-transistor-array fabrication method, and display device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/144162 | Thin-film-transistor-array substrate, thin-film-transistor-array fabrication method, and display device | May 9, 2002 | Issued |