Search

Lan Vinh

Examiner (ID: 2362, Phone: (571)272-1471 , Office: P/1713 )

Most Active Art Unit
1713
Art Unit(s)
1765, 1792, 1713
Total Applications
1662
Issued Applications
1401
Pending Applications
46
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7365827 [patent_doc_number] => 20040005787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Method to reduce residual particulate contamination in CVD and PVD semiconductor wafer manufacturing' [patent_app_type] => new [patent_app_number] => 10/188490 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4048 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20040005787.pdf [firstpage_image] =>[orig_patent_app_number] => 10188490 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/188490
Method to reduce residual particulate contamination in CVD and PVD semiconductor wafer manufacturing Jul 1, 2002 Issued
Array ( [id] => 7356115 [patent_doc_number] => 20040004056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'Method of etching a film of magnetic material and method of manufacturing a thin-film magnetic head' [patent_app_type] => new [patent_app_number] => 10/186428 [patent_app_country] => US [patent_app_date] => 2002-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 21320 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20040004056.pdf [firstpage_image] =>[orig_patent_app_number] => 10186428 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/186428
Method of etching a film of magnetic material and method of manufacturing a thin-film magnetic head Jul 1, 2002 Issued
Array ( [id] => 1130586 [patent_doc_number] => 06787471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => B2 [patent_app_number] => 10/184898 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 42 [patent_no_of_words] => 7979 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/787/06787471.pdf [firstpage_image] =>[orig_patent_app_number] => 10184898 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184898
Method of manufacturing a semiconductor device Jun 30, 2002 Issued
Array ( [id] => 620091 [patent_doc_number] => 07141506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'Method for evaluating dependence of properties of semiconductor substrate on plane orientation and semiconductor device using the same' [patent_app_type] => utility [patent_app_number] => 10/175076 [patent_app_country] => US [patent_app_date] => 2002-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 31 [patent_no_of_words] => 5953 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/141/07141506.pdf [firstpage_image] =>[orig_patent_app_number] => 10175076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/175076
Method for evaluating dependence of properties of semiconductor substrate on plane orientation and semiconductor device using the same Jun 19, 2002 Issued
Array ( [id] => 1071501 [patent_doc_number] => 06841082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Method of manufacturing Er-doped silicon nano-dot array and laser ablation appparatus used therein' [patent_app_type] => utility [patent_app_number] => 10/171751 [patent_app_country] => US [patent_app_date] => 2002-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3759 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841082.pdf [firstpage_image] =>[orig_patent_app_number] => 10171751 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/171751
Method of manufacturing Er-doped silicon nano-dot array and laser ablation appparatus used therein Jun 11, 2002 Issued
Array ( [id] => 7344359 [patent_doc_number] => 20040192056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Dry-etcching method' [patent_app_type] => new [patent_app_number] => 10/480821 [patent_app_country] => US [patent_app_date] => 2003-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6850 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0192/20040192056.pdf [firstpage_image] =>[orig_patent_app_number] => 10480821 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/480821
Dry-etching method Jun 6, 2002 Issued
Array ( [id] => 6838938 [patent_doc_number] => 20030036278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Method for fabricating a gate stack in very large scale integrated semiconductor memories' [patent_app_type] => new [patent_app_number] => 10/159155 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1637 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20030036278.pdf [firstpage_image] =>[orig_patent_app_number] => 10159155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/159155
Method for fabricating a gate stack in very large scale integrated semiconductor memories May 30, 2002 Issued
Array ( [id] => 1119891 [patent_doc_number] => 06797636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Process of fabricating DRAM cells with collar isolation layers' [patent_app_type] => B2 [patent_app_number] => 10/157870 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2712 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797636.pdf [firstpage_image] =>[orig_patent_app_number] => 10157870 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/157870
Process of fabricating DRAM cells with collar isolation layers May 30, 2002 Issued
Array ( [id] => 1059551 [patent_doc_number] => 06852641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Method of spiking mixed acid liquid in reactor' [patent_app_type] => utility [patent_app_number] => 10/063975 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 21 [patent_no_of_words] => 3443 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/852/06852641.pdf [firstpage_image] =>[orig_patent_app_number] => 10063975 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/063975
Method of spiking mixed acid liquid in reactor May 29, 2002 Issued
Array ( [id] => 1126743 [patent_doc_number] => 06790782 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-14 [patent_title] => 'Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal' [patent_app_type] => B1 [patent_app_number] => 10/157450 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 6234 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/790/06790782.pdf [firstpage_image] =>[orig_patent_app_number] => 10157450 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/157450
Process for fabrication of a transistor gate including high-K gate dielectric with in-situ resist trim, gate etch, and high-K dielectric removal May 28, 2002 Issued
Array ( [id] => 6260713 [patent_doc_number] => 20020187637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Polishing method using ceria slurry, and method of manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/156014 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3503 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20020187637.pdf [firstpage_image] =>[orig_patent_app_number] => 10156014 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/156014
Polishing method using ceria slurry, and method of manufacturing semiconductor device May 28, 2002 Issued
Array ( [id] => 6701703 [patent_doc_number] => 20030224583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Method for plasma etching a wafer after backside grinding' [patent_app_type] => new [patent_app_number] => 10/157683 [patent_app_country] => US [patent_app_date] => 2002-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20030224583.pdf [firstpage_image] =>[orig_patent_app_number] => 10157683 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/157683
Method for plasma etching a wafer after backside grinding May 28, 2002 Issued
Array ( [id] => 5900176 [patent_doc_number] => 20020139665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-03 [patent_title] => 'Plasma etch reactor and method' [patent_app_type] => new [patent_app_number] => 10/156478 [patent_app_country] => US [patent_app_date] => 2002-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6132 [patent_no_of_claims] => 116 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20020139665.pdf [firstpage_image] =>[orig_patent_app_number] => 10156478 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/156478
Plasma etch reactor and method May 27, 2002 Issued
Array ( [id] => 6701730 [patent_doc_number] => 20030224610 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-04 [patent_title] => 'Fabrication process for bonded wafer precision layer thickness control and its non-destructructive measurement method' [patent_app_type] => new [patent_app_number] => 10/155008 [patent_app_country] => US [patent_app_date] => 2002-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2477 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20030224610.pdf [firstpage_image] =>[orig_patent_app_number] => 10155008 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155008
Fabrication process for bonded wafer precision layer thickness control and its non-destructive measurement method May 27, 2002 Issued
Array ( [id] => 1123458 [patent_doc_number] => 06794289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-21 [patent_title] => 'Method and apparatuses for making and using bi-modal abrasive slurries for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies' [patent_app_type] => B2 [patent_app_number] => 10/155203 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4361 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794289.pdf [firstpage_image] =>[orig_patent_app_number] => 10155203 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155203
Method and apparatuses for making and using bi-modal abrasive slurries for mechanical and chemical-mechanical planarization of microelectronic-device substrate assemblies May 22, 2002 Issued
Array ( [id] => 6425482 [patent_doc_number] => 20020175140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method for forming metal layer of semiconductor device' [patent_app_type] => new [patent_app_number] => 10/154078 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2297 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20020175140.pdf [firstpage_image] =>[orig_patent_app_number] => 10154078 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/154078
Method for forming metal layer of semiconductor device May 22, 2002 Issued
Array ( [id] => 6865288 [patent_doc_number] => 20030190814 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Method of reducing micromasking during plasma etching of a silicon-comprising substrate' [patent_app_type] => new [patent_app_number] => 10/155424 [patent_app_country] => US [patent_app_date] => 2002-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4794 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20030190814.pdf [firstpage_image] =>[orig_patent_app_number] => 10155424 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155424
Method of reducing micromasking during plasma etching of a silicon-comprising substrate May 22, 2002 Abandoned
Array ( [id] => 6770022 [patent_doc_number] => 20030215962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Integration of multiple processes within a single chamber' [patent_app_type] => new [patent_app_number] => 10/146324 [patent_app_country] => US [patent_app_date] => 2002-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2669 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0215/20030215962.pdf [firstpage_image] =>[orig_patent_app_number] => 10146324 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/146324
Integration of multiple processes within a single chamber May 13, 2002 Abandoned
Array ( [id] => 6048226 [patent_doc_number] => 20020168851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => ' Method of forming silicidation blocking layer' [patent_app_type] => new [patent_app_number] => 10/142496 [patent_app_country] => US [patent_app_date] => 2002-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3436 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20020168851.pdf [firstpage_image] =>[orig_patent_app_number] => 10142496 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/142496
Method of forming silicidation blocking layer May 9, 2002 Issued
Array ( [id] => 1092936 [patent_doc_number] => 06825125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Thin-film-transistor-array substrate, thin-film-transistor-array fabrication method, and display device' [patent_app_type] => B2 [patent_app_number] => 10/144162 [patent_app_country] => US [patent_app_date] => 2002-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 13 [patent_no_of_words] => 6410 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/825/06825125.pdf [firstpage_image] =>[orig_patent_app_number] => 10144162 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/144162
Thin-film-transistor-array substrate, thin-film-transistor-array fabrication method, and display device May 9, 2002 Issued
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