
Lan Vinh
Examiner (ID: 2362, Phone: (571)272-1471 , Office: P/1713 )
| Most Active Art Unit | 1713 |
| Art Unit(s) | 1765, 1792, 1713 |
| Total Applications | 1662 |
| Issued Applications | 1401 |
| Pending Applications | 46 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 668463
[patent_doc_number] => 07094704
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-22
[patent_title] => 'Method of plasma etching of high-K dielectric materials'
[patent_app_type] => utility
[patent_app_number] => 10/143397
[patent_app_country] => US
[patent_app_date] => 2002-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2945
[patent_no_of_claims] => 42
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/094/07094704.pdf
[firstpage_image] =>[orig_patent_app_number] => 10143397
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/143397 | Method of plasma etching of high-K dielectric materials | May 8, 2002 | Issued |
Array
(
[id] => 6730367
[patent_doc_number] => 20030186557
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-10-02
[patent_title] => 'Fabrication method for lines of semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/142696
[patent_app_country] => US
[patent_app_date] => 2002-05-08
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0186/20030186557.pdf
[firstpage_image] =>[orig_patent_app_number] => 10142696
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/142696 | Fabrication method for lines of semiconductor device | May 7, 2002 | Issued |
Array
(
[id] => 1043711
[patent_doc_number] => 06867144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-03-15
[patent_title] => 'Apparatus and method for plasma processing high-speed semiconductor circuits with increased yield'
[patent_app_type] => utility
[patent_app_number] => 10/138635
[patent_app_country] => US
[patent_app_date] => 2002-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/06/867/06867144.pdf
[firstpage_image] =>[orig_patent_app_number] => 10138635
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/138635 | Apparatus and method for plasma processing high-speed semiconductor circuits with increased yield | May 5, 2002 | Issued |
Array
(
[id] => 1101796
[patent_doc_number] => 06815362
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-11-09
[patent_title] => 'End point determination of process residues in wafer-less auto clean process using optical emission spectroscopy'
[patent_app_type] => B1
[patent_app_number] => 10/138980
[patent_app_country] => US
[patent_app_date] => 2002-05-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 8770
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[pdf_file] => patents/06/815/06815362.pdf
[firstpage_image] =>[orig_patent_app_number] => 10138980
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/138980 | End point determination of process residues in wafer-less auto clean process using optical emission spectroscopy | May 2, 2002 | Issued |
Array
(
[id] => 1165656
[patent_doc_number] => 06756313
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-06-29
[patent_title] => 'Method of etching silicon nitride spacers with high selectivity relative to oxide in a high density plasma chamber'
[patent_app_type] => B2
[patent_app_number] => 10/139663
[patent_app_country] => US
[patent_app_date] => 2002-05-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/756/06756313.pdf
[firstpage_image] =>[orig_patent_app_number] => 10139663
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/139663 | Method of etching silicon nitride spacers with high selectivity relative to oxide in a high density plasma chamber | May 1, 2002 | Issued |
Array
(
[id] => 6636703
[patent_doc_number] => 20030211752
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-11-13
[patent_title] => 'Method of smoothing a trench sidewall after a deep trench silicon etch process'
[patent_app_type] => new
[patent_app_number] => 10/137543
[patent_app_country] => US
[patent_app_date] => 2002-05-01
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[pdf_file] => publications/A1/0211/20030211752.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/137543 | Method of smoothing a trench sidewall after a deep trench silicon etch process | Apr 30, 2002 | Issued |
Array
(
[id] => 1062810
[patent_doc_number] => 06849554
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-02-01
[patent_title] => 'Method of etching a deep trench having a tapered profile in silicon'
[patent_app_type] => utility
[patent_app_number] => 10/137176
[patent_app_country] => US
[patent_app_date] => 2002-05-01
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/137176 | Method of etching a deep trench having a tapered profile in silicon | Apr 30, 2002 | Issued |
Array
(
[id] => 1034490
[patent_doc_number] => 06875699
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-05
[patent_title] => 'Method for patterning multilevel interconnects'
[patent_app_type] => utility
[patent_app_number] => 10/138041
[patent_app_country] => US
[patent_app_date] => 2002-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] => patents/06/875/06875699.pdf
[firstpage_image] =>[orig_patent_app_number] => 10138041
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/138041 | Method for patterning multilevel interconnects | Apr 30, 2002 | Issued |
Array
(
[id] => 1175466
[patent_doc_number] => 06746963
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[patent_kind] => B2
[patent_issue_date] => 2004-06-08
[patent_title] => 'Method for processing coating film and method for manufacturing semiconductor element with use of the same method'
[patent_app_type] => B2
[patent_app_number] => 10/136744
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/136744 | Method for processing coating film and method for manufacturing semiconductor element with use of the same method | Apr 29, 2002 | Issued |
Array
(
[id] => 1105037
[patent_doc_number] => 06812153
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-11-02
[patent_title] => 'Method for high aspect ratio HDP CVD gapfill'
[patent_app_type] => B2
[patent_app_number] => 10/137132
[patent_app_country] => US
[patent_app_date] => 2002-04-30
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/812/06812153.pdf
[firstpage_image] =>[orig_patent_app_number] => 10137132
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/137132 | Method for high aspect ratio HDP CVD gapfill | Apr 29, 2002 | Issued |
Array
(
[id] => 6772155
[patent_doc_number] => 20030015493
[patent_country] => US
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[patent_issue_date] => 2003-01-23
[patent_title] => 'System and method for wafer-based controlled patterning of features with critical dimensions'
[patent_app_type] => new
[patent_app_number] => 10/128662
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[patent_app_date] => 2002-04-22
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/128662 | System and method for wafer-based controlled patterning of features with critical dimensions | Apr 21, 2002 | Issued |
Array
(
[id] => 6169495
[patent_doc_number] => 20020153348
[patent_country] => US
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[patent_issue_date] => 2002-10-24
[patent_title] => 'Orthopedic implant having a porous surface and method of making same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/118166 | Orthopedic implant having a porous surface and method of making same | Apr 8, 2002 | Abandoned |
Array
(
[id] => 6521567
[patent_doc_number] => 20020109122
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[patent_issue_date] => 2002-08-15
[patent_title] => 'Fixed-abrasive chemical-mechanical planarization of titanium nitride'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/116306 | Fixed-abrasive chemical-mechanical planarization of titanium nitride | Apr 3, 2002 | Abandoned |
Array
(
[id] => 1009055
[patent_doc_number] => 06899815
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[patent_issue_date] => 2005-05-31
[patent_title] => 'Multi-layer integrated circuit package'
[patent_app_type] => utility
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[firstpage_image] =>[orig_patent_app_number] => 10109792
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/109792 | Multi-layer integrated circuit package | Mar 28, 2002 | Issued |
Array
(
[id] => 6829994
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[patent_title] => 'Method of forming integrated circuit structures in silicone ladder polymer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/101750 | Method of forming integrated circuit structures in silicone ladder polymer | Mar 20, 2002 | Issued |
Array
(
[id] => 307039
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[patent_title] => 'Micro-optic elements and method for making the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/104900 | Micro-optic elements and method for making the same | Mar 19, 2002 | Issued |
Array
(
[id] => 6711251
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Array
(
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Array
(
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Array
(
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[patent_title] => 'Multi-layer film stack polish stop'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/072160 | Multi-layer film stack polish stop | Feb 4, 2002 | Issued |