
Lan Vinh
Examiner (ID: 2362, Phone: (571)272-1471 , Office: P/1713 )
| Most Active Art Unit | 1713 |
| Art Unit(s) | 1765, 1792, 1713 |
| Total Applications | 1662 |
| Issued Applications | 1401 |
| Pending Applications | 46 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1534664
[patent_doc_number] => 06489245
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-03
[patent_title] => 'Methods for reducing mask erosion during plasma etching'
[patent_app_type] => B1
[patent_app_number] => 09/610303
[patent_app_country] => US
[patent_app_date] => 2000-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5083
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/489/06489245.pdf
[firstpage_image] =>[orig_patent_app_number] => 09610303
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/610303 | Methods for reducing mask erosion during plasma etching | Jul 4, 2000 | Issued |
Array
(
[id] => 1561253
[patent_doc_number] => 06362109
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Oxide/nitride etching having high selectivity to photoresist'
[patent_app_type] => B1
[patent_app_number] => 09/585632
[patent_app_country] => US
[patent_app_date] => 2000-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3611
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/362/06362109.pdf
[firstpage_image] =>[orig_patent_app_number] => 09585632
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/585632 | Oxide/nitride etching having high selectivity to photoresist | Jun 1, 2000 | Issued |
Array
(
[id] => 1030706
[patent_doc_number] => 06878297
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-04-12
[patent_title] => 'Method of producing organic light-emissive devices'
[patent_app_type] => utility
[patent_app_number] => 10/009078
[patent_app_country] => US
[patent_app_date] => 2000-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 6144
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/878/06878297.pdf
[firstpage_image] =>[orig_patent_app_number] => 10009078
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/009078 | Method of producing organic light-emissive devices | May 31, 2000 | Issued |
Array
(
[id] => 1528143
[patent_doc_number] => 06479385
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-12
[patent_title] => 'Interlevel dielectric composite layer for insulation of polysilicon and metal structures'
[patent_app_type] => B1
[patent_app_number] => 09/583397
[patent_app_country] => US
[patent_app_date] => 2000-05-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 2283
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/479/06479385.pdf
[firstpage_image] =>[orig_patent_app_number] => 09583397
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/583397 | Interlevel dielectric composite layer for insulation of polysilicon and metal structures | May 30, 2000 | Issued |
Array
(
[id] => 1123475
[patent_doc_number] => 06794295
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-09-21
[patent_title] => 'Method to improve stability and reliability of CVD low K dielectric'
[patent_app_type] => B1
[patent_app_number] => 09/579542
[patent_app_country] => US
[patent_app_date] => 2000-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 5
[patent_no_of_words] => 1981
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/794/06794295.pdf
[firstpage_image] =>[orig_patent_app_number] => 09579542
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/579542 | Method to improve stability and reliability of CVD low K dielectric | May 25, 2000 | Issued |
Array
(
[id] => 4417667
[patent_doc_number] => 06194326
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-27
[patent_title] => 'Low temperature rinse of etching agents'
[patent_app_type] => 1
[patent_app_number] => 9/544721
[patent_app_country] => US
[patent_app_date] => 2000-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 3254
[patent_no_of_claims] => 36
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/194/06194326.pdf
[firstpage_image] =>[orig_patent_app_number] => 544721
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/544721 | Low temperature rinse of etching agents | Apr 5, 2000 | Issued |
Array
(
[id] => 6306884
[patent_doc_number] => 20020094693
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-07-18
[patent_title] => 'Method for fabricating an ultra small opening'
[patent_app_type] => new
[patent_app_number] => 09/532282
[patent_app_country] => US
[patent_app_date] => 2000-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1984
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0094/20020094693.pdf
[firstpage_image] =>[orig_patent_app_number] => 09532282
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/532282 | Method for fabricating an ultra small opening | Mar 22, 2000 | Issued |
Array
(
[id] => 1583082
[patent_doc_number] => 06424039
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-07-23
[patent_title] => 'Dual damascene process using sacrificial spin-on materials'
[patent_app_type] => B1
[patent_app_number] => 09/532731
[patent_app_country] => US
[patent_app_date] => 2000-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 22
[patent_no_of_words] => 2025
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/424/06424039.pdf
[firstpage_image] =>[orig_patent_app_number] => 09532731
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/532731 | Dual damascene process using sacrificial spin-on materials | Mar 21, 2000 | Issued |
Array
(
[id] => 1532657
[patent_doc_number] => 06410439
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-25
[patent_title] => 'Semiconductor polishing apparatus and method for chemical/mechanical polishing of films'
[patent_app_type] => B1
[patent_app_number] => 09/527528
[patent_app_country] => US
[patent_app_date] => 2000-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3600
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/410/06410439.pdf
[firstpage_image] =>[orig_patent_app_number] => 09527528
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/527528 | Semiconductor polishing apparatus and method for chemical/mechanical polishing of films | Mar 15, 2000 | Issued |
Array
(
[id] => 7636563
[patent_doc_number] => 06380092
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-30
[patent_title] => 'Gas phase planarization process for semiconductor wafers'
[patent_app_type] => B1
[patent_app_number] => 09/516333
[patent_app_country] => US
[patent_app_date] => 2000-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 7750
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/380/06380092.pdf
[firstpage_image] =>[orig_patent_app_number] => 09516333
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/516333 | Gas phase planarization process for semiconductor wafers | Feb 29, 2000 | Issued |
Array
(
[id] => 5828840
[patent_doc_number] => 20020068462
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-06
[patent_title] => 'Method of etching a material layer and forming a lithography mask for use in manufacturing a microstructure'
[patent_app_type] => new
[patent_app_number] => 09/513796
[patent_app_country] => US
[patent_app_date] => 2000-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4311
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 43
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0068/20020068462.pdf
[firstpage_image] =>[orig_patent_app_number] => 09513796
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/513796 | Method of etching a material layer and forming a lithography mask for use in manufacturing a microstructure | Feb 24, 2000 | Abandoned |
Array
(
[id] => 1561241
[patent_doc_number] => 06362104
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Method for polishing a substrate using a CMP slurry'
[patent_app_type] => B1
[patent_app_number] => 09/501221
[patent_app_country] => US
[patent_app_date] => 2000-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7464
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/362/06362104.pdf
[firstpage_image] =>[orig_patent_app_number] => 09501221
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/501221 | Method for polishing a substrate using a CMP slurry | Feb 9, 2000 | Issued |
Array
(
[id] => 1600548
[patent_doc_number] => 06475916
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-11-05
[patent_title] => 'Method of patterning gate electrode with ultra-thin gate dielectric'
[patent_app_type] => B1
[patent_app_number] => 09/483936
[patent_app_country] => US
[patent_app_date] => 2000-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 20
[patent_no_of_words] => 5466
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 307
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/475/06475916.pdf
[firstpage_image] =>[orig_patent_app_number] => 09483936
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/483936 | Method of patterning gate electrode with ultra-thin gate dielectric | Jan 17, 2000 | Issued |
Array
(
[id] => 1303140
[patent_doc_number] => 06620738
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-09-16
[patent_title] => 'Etchant and method for fabricating a semiconductor device using the same'
[patent_app_type] => B2
[patent_app_number] => 09/484473
[patent_app_country] => US
[patent_app_date] => 2000-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 2374
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/620/06620738.pdf
[firstpage_image] =>[orig_patent_app_number] => 09484473
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/484473 | Etchant and method for fabricating a semiconductor device using the same | Jan 17, 2000 | Issued |
Array
(
[id] => 1561239
[patent_doc_number] => 06362103
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-03-26
[patent_title] => 'Method and apparatus for rejuvenating a CMP chemical solution'
[patent_app_type] => B1
[patent_app_number] => 09/484933
[patent_app_country] => US
[patent_app_date] => 2000-01-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 7
[patent_no_of_words] => 4505
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/362/06362103.pdf
[firstpage_image] =>[orig_patent_app_number] => 09484933
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/484933 | Method and apparatus for rejuvenating a CMP chemical solution | Jan 17, 2000 | Issued |
Array
(
[id] => 7643901
[patent_doc_number] => 06429137
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Solid state thermal switch'
[patent_app_type] => B1
[patent_app_number] => 09/479097
[patent_app_country] => US
[patent_app_date] => 2000-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 4744
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 17
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/429/06429137.pdf
[firstpage_image] =>[orig_patent_app_number] => 09479097
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/479097 | Solid state thermal switch | Jan 6, 2000 | Issued |
Array
(
[id] => 1450120
[patent_doc_number] => 06455436
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-09-24
[patent_title] => 'Method of fabricating semiconductor device'
[patent_app_type] => B1
[patent_app_number] => 09/479243
[patent_app_country] => US
[patent_app_date] => 2000-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 97
[patent_no_of_words] => 11087
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 438
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/455/06455436.pdf
[firstpage_image] =>[orig_patent_app_number] => 09479243
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/479243 | Method of fabricating semiconductor device | Jan 6, 2000 | Issued |
Array
(
[id] => 1550549
[patent_doc_number] => 06399508
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-06-04
[patent_title] => 'Method for metal etch using a dielectric hard mask'
[patent_app_type] => B1
[patent_app_number] => 09/479404
[patent_app_country] => US
[patent_app_date] => 2000-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3661
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/399/06399508.pdf
[firstpage_image] =>[orig_patent_app_number] => 09479404
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/479404 | Method for metal etch using a dielectric hard mask | Jan 5, 2000 | Issued |
Array
(
[id] => 7643894
[patent_doc_number] => 06429144
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-08-06
[patent_title] => 'Integrated circuit manufacture method with aqueous hydrogen fluoride and nitric acid oxide etch'
[patent_app_type] => B1
[patent_app_number] => 09/473451
[patent_app_country] => US
[patent_app_date] => 1999-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3553
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 13
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/429/06429144.pdf
[firstpage_image] =>[orig_patent_app_number] => 09473451
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/473451 | Integrated circuit manufacture method with aqueous hydrogen fluoride and nitric acid oxide etch | Dec 27, 1999 | Issued |
Array
(
[id] => 1163573
[patent_doc_number] => 06759337
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-07-06
[patent_title] => 'Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate'
[patent_app_type] => B1
[patent_app_number] => 09/464297
[patent_app_country] => US
[patent_app_date] => 1999-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2113
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 198
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/759/06759337.pdf
[firstpage_image] =>[orig_patent_app_number] => 09464297
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/464297 | Process for etching a controllable thickness of oxide on an integrated circuit structure on a semiconductor substrate using nitrogen plasma and plasma and an rf bias applied to the substrate | Dec 14, 1999 | Issued |