
Lan Vinh
Examiner (ID: 2362, Phone: (571)272-1471 , Office: P/1713 )
| Most Active Art Unit | 1713 |
| Art Unit(s) | 1765, 1792, 1713 |
| Total Applications | 1662 |
| Issued Applications | 1401 |
| Pending Applications | 46 |
| Abandoned Applications | 218 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7637013
[patent_doc_number] => 06379642
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-30
[patent_title] => 'Vacancy dominated, defect-free silicon'
[patent_app_type] => B1
[patent_app_number] => 09/270366
[patent_app_country] => US
[patent_app_date] => 1999-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
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[patent_no_of_words] => 13707
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/379/06379642.pdf
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Array
(
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[patent_kind] => A1
[patent_issue_date] => 2001-07-19
[patent_title] => 'PLASMA SURFACE TREATMENT METHOD AND RESULTING DEVICE'
[patent_app_type] => new-utility
[patent_app_number] => 09/268203
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[patent_app_date] => 1999-03-15
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/268203 | Plasma surface treatment method and resulting device | Mar 14, 1999 | Issued |
Array
(
[id] => 4395561
[patent_doc_number] => 06297160
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[patent_kind] => NA
[patent_issue_date] => 2001-10-02
[patent_title] => 'Application of pure aluminum to prevent pad corrosion'
[patent_app_type] => 1
[patent_app_number] => 9/266881
[patent_app_country] => US
[patent_app_date] => 1999-03-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/266881 | Application of pure aluminum to prevent pad corrosion | Mar 11, 1999 | Issued |
Array
(
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[patent_doc_number] => 06495465
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[patent_issue_date] => 2002-12-17
[patent_title] => 'Method for appraising the condition of a semiconductor polishing cloth'
[patent_app_type] => B2
[patent_app_number] => 09/266051
[patent_app_country] => US
[patent_app_date] => 1999-03-10
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/266051 | Method for appraising the condition of a semiconductor polishing cloth | Mar 9, 1999 | Issued |
Array
(
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[patent_issue_date] => 2003-12-09
[patent_title] => 'Etching of semiconductor wafer edges'
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[patent_app_number] => 09/261616
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/261616 | Etching of semiconductor wafer edges | Mar 2, 1999 | Issued |
Array
(
[id] => 1245774
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[patent_issue_date] => 2004-01-13
[patent_title] => 'Method for manufacturing breakaway layers for detaching deposited layer systems'
[patent_app_type] => B2
[patent_app_number] => 09/238959
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/238959 | Method for manufacturing breakaway layers for detaching deposited layer systems | Jan 26, 1999 | Issued |
Array
(
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[patent_title] => 'Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer'
[patent_app_type] => B1
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Array
(
[id] => 4406499
[patent_doc_number] => 06171970
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[patent_issue_date] => 2001-01-09
[patent_title] => 'Method for forming high-density integrated circuit capacitors'
[patent_app_type] => 1
[patent_app_number] => 9/238211
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[firstpage_image] =>[orig_patent_app_number] => 238211
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/238211 | Method for forming high-density integrated circuit capacitors | Jan 26, 1999 | Issued |
Array
(
[id] => 4250812
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Array
(
[id] => 1310868
[patent_doc_number] => 06613676
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[patent_issue_date] => 2003-09-02
[patent_title] => 'Process of reclamation of SOI substrate and reproduced substrate'
[patent_app_type] => B1
[patent_app_number] => 09/238500
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Array
(
[id] => 4348736
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[patent_title] => 'Simplified sidewall formation for sidewall patterning of sub 100 nm structures'
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Array
(
[id] => 1566121
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Array
(
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Array
(
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Array
(
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Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/231537 | Process for removing photoresist material | Jan 13, 1999 | Issued |
Array
(
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Array
(
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Array
(
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[patent_title] => 'METHOD OF PLASMA ETCHING DOPED POLYSILICON LAYERS WITH UNIFORM ETCH RATES'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/213611 | METHOD OF PLASMA ETCHING DOPED POLYSILICON LAYERS WITH UNIFORM ETCH RATES | Dec 17, 1998 | Abandoned |