Search

Lan Vinh

Examiner (ID: 2362, Phone: (571)272-1471 , Office: P/1713 )

Most Active Art Unit
1713
Art Unit(s)
1765, 1792, 1713
Total Applications
1662
Issued Applications
1401
Pending Applications
46
Abandoned Applications
218

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7637013 [patent_doc_number] => 06379642 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Vacancy dominated, defect-free silicon' [patent_app_type] => B1 [patent_app_number] => 09/270366 [patent_app_country] => US [patent_app_date] => 1999-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 26 [patent_no_of_words] => 13707 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/379/06379642.pdf [firstpage_image] =>[orig_patent_app_number] => 09270366 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/270366
Vacancy dominated, defect-free silicon Mar 15, 1999 Issued
Array ( [id] => 6887809 [patent_doc_number] => 20010008803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-19 [patent_title] => 'PLASMA SURFACE TREATMENT METHOD AND RESULTING DEVICE' [patent_app_type] => new-utility [patent_app_number] => 09/268203 [patent_app_country] => US [patent_app_date] => 1999-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20010008803.pdf [firstpage_image] =>[orig_patent_app_number] => 09268203 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/268203
Plasma surface treatment method and resulting device Mar 14, 1999 Issued
Array ( [id] => 4395561 [patent_doc_number] => 06297160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Application of pure aluminum to prevent pad corrosion' [patent_app_type] => 1 [patent_app_number] => 9/266881 [patent_app_country] => US [patent_app_date] => 1999-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1707 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297160.pdf [firstpage_image] =>[orig_patent_app_number] => 266881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/266881
Application of pure aluminum to prevent pad corrosion Mar 11, 1999 Issued
Array ( [id] => 1440141 [patent_doc_number] => 06495465 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Method for appraising the condition of a semiconductor polishing cloth' [patent_app_type] => B2 [patent_app_number] => 09/266051 [patent_app_country] => US [patent_app_date] => 1999-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1613 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495465.pdf [firstpage_image] =>[orig_patent_app_number] => 09266051 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/266051
Method for appraising the condition of a semiconductor polishing cloth Mar 9, 1999 Issued
Array ( [id] => 1264573 [patent_doc_number] => 06660643 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-09 [patent_title] => 'Etching of semiconductor wafer edges' [patent_app_type] => B1 [patent_app_number] => 09/261616 [patent_app_country] => US [patent_app_date] => 1999-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4778 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/660/06660643.pdf [firstpage_image] =>[orig_patent_app_number] => 09261616 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261616
Etching of semiconductor wafer edges Mar 2, 1999 Issued
Array ( [id] => 1245774 [patent_doc_number] => 06677249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Method for manufacturing breakaway layers for detaching deposited layer systems' [patent_app_type] => B2 [patent_app_number] => 09/238959 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1637 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677249.pdf [firstpage_image] =>[orig_patent_app_number] => 09238959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238959
Method for manufacturing breakaway layers for detaching deposited layer systems Jan 26, 1999 Issued
Array ( [id] => 7636564 [patent_doc_number] => 06380091 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-30 [patent_title] => 'Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer' [patent_app_type] => B1 [patent_app_number] => 09/238050 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3971 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/380/06380091.pdf [firstpage_image] =>[orig_patent_app_number] => 09238050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238050
Dual damascene arrangement for metal interconnection with oxide dielectric layer and low K dielectric constant layer Jan 26, 1999 Issued
Array ( [id] => 4406499 [patent_doc_number] => 06171970 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method for forming high-density integrated circuit capacitors' [patent_app_type] => 1 [patent_app_number] => 9/238211 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 30 [patent_no_of_words] => 4974 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171970.pdf [firstpage_image] =>[orig_patent_app_number] => 238211 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238211
Method for forming high-density integrated circuit capacitors Jan 26, 1999 Issued
Array ( [id] => 4250812 [patent_doc_number] => 06207577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer' [patent_app_type] => 1 [patent_app_number] => 9/238049 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4024 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207577.pdf [firstpage_image] =>[orig_patent_app_number] => 238049 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238049
Self-aligned dual damascene arrangement for metal interconnection with oxide dielectric layer and low k dielectric constant layer Jan 26, 1999 Issued
Array ( [id] => 1310868 [patent_doc_number] => 06613676 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Process of reclamation of SOI substrate and reproduced substrate' [patent_app_type] => B1 [patent_app_number] => 09/238500 [patent_app_country] => US [patent_app_date] => 1999-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 36 [patent_no_of_words] => 8020 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/613/06613676.pdf [firstpage_image] =>[orig_patent_app_number] => 09238500 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/238500
Process of reclamation of SOI substrate and reproduced substrate Jan 26, 1999 Issued
Array ( [id] => 4348736 [patent_doc_number] => 06214737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Simplified sidewall formation for sidewall patterning of sub 100 nm structures' [patent_app_type] => 1 [patent_app_number] => 9/234379 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 4734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214737.pdf [firstpage_image] =>[orig_patent_app_number] => 234379 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/234379
Simplified sidewall formation for sidewall patterning of sub 100 nm structures Jan 19, 1999 Issued
Array ( [id] => 1566121 [patent_doc_number] => 06376383 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-23 [patent_title] => 'Method for etching silicon layer' [patent_app_type] => B2 [patent_app_number] => 09/233089 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 3067 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376383.pdf [firstpage_image] =>[orig_patent_app_number] => 09233089 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233089
Method for etching silicon layer Jan 18, 1999 Issued
Array ( [id] => 4108151 [patent_doc_number] => 06057245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Gas phase planarization process for semiconductor wafers' [patent_app_type] => 1 [patent_app_number] => 9/233640 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7732 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057245.pdf [firstpage_image] =>[orig_patent_app_number] => 233640 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233640
Gas phase planarization process for semiconductor wafers Jan 18, 1999 Issued
Array ( [id] => 1105014 [patent_doc_number] => 06812151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-02 [patent_title] => 'Method of etching' [patent_app_type] => B1 [patent_app_number] => 09/233073 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 3876 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/812/06812151.pdf [firstpage_image] =>[orig_patent_app_number] => 09233073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/233073
Method of etching Jan 18, 1999 Issued
Array ( [id] => 4130526 [patent_doc_number] => 06033987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Method for mapping and adjusting pressure distribution of CMP processes' [patent_app_type] => 1 [patent_app_number] => 9/232179 [patent_app_country] => US [patent_app_date] => 1999-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2136 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/033/06033987.pdf [firstpage_image] =>[orig_patent_app_number] => 232179 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/232179
Method for mapping and adjusting pressure distribution of CMP processes Jan 14, 1999 Issued
Array ( [id] => 1439034 [patent_doc_number] => 06494984 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Flat media processing machine' [patent_app_type] => B2 [patent_app_number] => 09/231194 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 2794 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/494/06494984.pdf [firstpage_image] =>[orig_patent_app_number] => 09231194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231194
Flat media processing machine Jan 13, 1999 Issued
Array ( [id] => 7000655 [patent_doc_number] => 20010053604 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'PROCESS FOR REMOVING PHOTORESIST MATERIAL' [patent_app_type] => new [patent_app_number] => 09/231537 [patent_app_country] => US [patent_app_date] => 1999-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1174 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053604.pdf [firstpage_image] =>[orig_patent_app_number] => 09231537 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/231537
Process for removing photoresist material Jan 13, 1999 Issued
Array ( [id] => 1231478 [patent_doc_number] => 06693044 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-17 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/227577 [patent_app_country] => US [patent_app_date] => 1999-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 50 [patent_no_of_words] => 11965 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/693/06693044.pdf [firstpage_image] =>[orig_patent_app_number] => 09227577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/227577
Semiconductor device and method of manufacturing the same Jan 7, 1999 Issued
Array ( [id] => 7634767 [patent_doc_number] => 06656851 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Method for forming isolation film' [patent_app_type] => B1 [patent_app_number] => 09/223377 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 17 [patent_no_of_words] => 1785 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/656/06656851.pdf [firstpage_image] =>[orig_patent_app_number] => 09223377 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/223377
Method for forming isolation film Dec 29, 1998 Issued
Array ( [id] => 7118435 [patent_doc_number] => 20010001729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-24 [patent_title] => 'METHOD OF PLASMA ETCHING DOPED POLYSILICON LAYERS WITH UNIFORM ETCH RATES' [patent_app_type] => new-utility [patent_app_number] => 09/213611 [patent_app_country] => US [patent_app_date] => 1998-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2917 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0001/20010001729.pdf [firstpage_image] =>[orig_patent_app_number] => 09213611 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/213611
METHOD OF PLASMA ETCHING DOPED POLYSILICON LAYERS WITH UNIFORM ETCH RATES Dec 17, 1998 Abandoned
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