| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3501849
[patent_doc_number] => 05471622
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-28
[patent_title] => 'Run-time system having nodes for identifying parallel tasks in a logic program and searching for available nodes to execute the parallel tasks'
[patent_app_type] => 1
[patent_app_number] => 8/425712
[patent_app_country] => US
[patent_app_date] => 1995-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 7884
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 309
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/471/05471622.pdf
[firstpage_image] =>[orig_patent_app_number] => 425712
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/425712 | Run-time system having nodes for identifying parallel tasks in a logic program and searching for available nodes to execute the parallel tasks | Apr 19, 1995 | Issued |
Array
(
[id] => 3500971
[patent_doc_number] => 05475858
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-12
[patent_title] => 'Real time multiprocessor system having a write only data link connected to one of the ports of the memory of each of the processor nodes'
[patent_app_type] => 1
[patent_app_number] => 8/402763
[patent_app_country] => US
[patent_app_date] => 1995-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 11045
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/475/05475858.pdf
[firstpage_image] =>[orig_patent_app_number] => 402763
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/402763 | Real time multiprocessor system having a write only data link connected to one of the ports of the memory of each of the processor nodes | Mar 12, 1995 | Issued |
Array
(
[id] => 3440632
[patent_doc_number] => 05463740
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-31
[patent_title] => 'Data control device generating different types of bus requests and transmitting requests directly to one of a number of arbiters for obtaining access to a respective bus'
[patent_app_type] => 1
[patent_app_number] => 8/387633
[patent_app_country] => US
[patent_app_date] => 1995-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 25
[patent_no_of_words] => 6181
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 295
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/463/05463740.pdf
[firstpage_image] =>[orig_patent_app_number] => 387633
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/387633 | Data control device generating different types of bus requests and transmitting requests directly to one of a number of arbiters for obtaining access to a respective bus | Feb 12, 1995 | Issued |
Array
(
[id] => 3602893
[patent_doc_number] => 05488720
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-30
[patent_title] => 'Apparatus with deletion safeguard for setting a number of data in temporary deletion state and independently releasing or deleting any one of the data'
[patent_app_type] => 1
[patent_app_number] => 8/385581
[patent_app_country] => US
[patent_app_date] => 1995-02-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 2485
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/488/05488720.pdf
[firstpage_image] =>[orig_patent_app_number] => 385581
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/385581 | Apparatus with deletion safeguard for setting a number of data in temporary deletion state and independently releasing or deleting any one of the data | Feb 7, 1995 | Issued |
Array
(
[id] => 3438969
[patent_doc_number] => 05455916
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-03
[patent_title] => 'Method for performing inter-unit data transfer operations among a plurality of input/output bus interface units coupled to a common asynchronous bus'
[patent_app_type] => 1
[patent_app_number] => 8/371041
[patent_app_country] => US
[patent_app_date] => 1995-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 41
[patent_figures_cnt] => 48
[patent_no_of_words] => 31738
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 414
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/455/05455916.pdf
[firstpage_image] =>[orig_patent_app_number] => 371041
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/371041 | Method for performing inter-unit data transfer operations among a plurality of input/output bus interface units coupled to a common asynchronous bus | Jan 9, 1995 | Issued |
Array
(
[id] => 3118568
[patent_doc_number] => 05448749
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-05
[patent_title] => 'Data processing apparatus with optical vector matrix multiplier and peripheral circuits'
[patent_app_type] => 1
[patent_app_number] => 8/366377
[patent_app_country] => US
[patent_app_date] => 1994-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 4036
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/448/05448749.pdf
[firstpage_image] =>[orig_patent_app_number] => 366377
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/366377 | Data processing apparatus with optical vector matrix multiplier and peripheral circuits | Dec 28, 1994 | Issued |
Array
(
[id] => 3495383
[patent_doc_number] => 05446878
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-29
[patent_title] => 'Method for selectively enabling subset of embedded event-making instructions and selecting types and items of event-based data to be collected per enabled instruction'
[patent_app_type] => 1
[patent_app_number] => 8/326815
[patent_app_country] => US
[patent_app_date] => 1994-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 7964
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 378
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/446/05446878.pdf
[firstpage_image] =>[orig_patent_app_number] => 326815
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/326815 | Method for selectively enabling subset of embedded event-making instructions and selecting types and items of event-based data to be collected per enabled instruction | Oct 19, 1994 | Issued |
| 08/290415 | COUPLED SYNCHRONOUS-ASYNCHRONOUS BUS STRUCTURE FOR TRANSFERRING DATA BETWEEN A PLURALITY OF PERIPHERAL INPUT/OUPUT CONTROLLERS AND A MAIN DATA STORE | Aug 14, 1994 | Abandoned |
Array
(
[id] => 3553560
[patent_doc_number] => 05481749
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-02
[patent_title] => 'Shift register divided into a number of cells and a number of stages within each cell to permit bit and multiple bit shifting'
[patent_app_type] => 1
[patent_app_number] => 8/289611
[patent_app_country] => US
[patent_app_date] => 1994-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 19
[patent_no_of_words] => 25571
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/481/05481749.pdf
[firstpage_image] =>[orig_patent_app_number] => 289611
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/289611 | Shift register divided into a number of cells and a number of stages within each cell to permit bit and multiple bit shifting | Aug 11, 1994 | Issued |
| 08/268158 | PARALLEL COMPUTING APPARATUS AND METHOD | Jun 27, 1994 | Abandoned |
Array
(
[id] => 3123389
[patent_doc_number] => 05465381
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-07
[patent_title] => 'Processor and read/write head incorporated in disk for communicating data to host directly from processor read/write head to read/write head of host disk drive'
[patent_app_type] => 1
[patent_app_number] => 8/254621
[patent_app_country] => US
[patent_app_date] => 1994-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 7525
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 245
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/465/05465381.pdf
[firstpage_image] =>[orig_patent_app_number] => 254621
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/254621 | Processor and read/write head incorporated in disk for communicating data to host directly from processor read/write head to read/write head of host disk drive | Jun 5, 1994 | Issued |
Array
(
[id] => 3438408
[patent_doc_number] => 05404517
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'Apparatus for assigning order for sequential display of randomly stored titles by comparing each of the titles and generating value indicating order based on the comparison'
[patent_app_type] => 1
[patent_app_number] => 8/240217
[patent_app_country] => US
[patent_app_date] => 1994-05-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 1780
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/404/05404517.pdf
[firstpage_image] =>[orig_patent_app_number] => 240217
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/240217 | Apparatus for assigning order for sequential display of randomly stored titles by comparing each of the titles and generating value indicating order based on the comparison | May 8, 1994 | Issued |
Array
(
[id] => 3549441
[patent_doc_number] => 05495619
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-27
[patent_title] => 'Apparatus providing addressable storage locations as virtual links and storing predefined destination information for any messages transmitted on virtual links at these locations'
[patent_app_type] => 1
[patent_app_number] => 8/229055
[patent_app_country] => US
[patent_app_date] => 1994-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 14274
[patent_no_of_claims] => 38
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 196
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/495/05495619.pdf
[firstpage_image] =>[orig_patent_app_number] => 229055
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/229055 | Apparatus providing addressable storage locations as virtual links and storing predefined destination information for any messages transmitted on virtual links at these locations | Apr 17, 1994 | Issued |
Array
(
[id] => 3553476
[patent_doc_number] => 05481746
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-02
[patent_title] => 'Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift counts stored in another vector register'
[patent_app_type] => 1
[patent_app_number] => 8/218997
[patent_app_country] => US
[patent_app_date] => 1994-03-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 6568
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/481/05481746.pdf
[firstpage_image] =>[orig_patent_app_number] => 218997
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/218997 | Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift counts stored in another vector register | Mar 28, 1994 | Issued |
Array
(
[id] => 3436091
[patent_doc_number] => 05423054
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-06
[patent_title] => 'Processor and read/write head incorporated in disk for communicating data to host directly from processor read/write head to read/write head of host disk drive'
[patent_app_type] => 1
[patent_app_number] => 8/185106
[patent_app_country] => US
[patent_app_date] => 1994-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 18
[patent_no_of_words] => 7530
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/423/05423054.pdf
[firstpage_image] =>[orig_patent_app_number] => 185106
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/185106 | Processor and read/write head incorporated in disk for communicating data to host directly from processor read/write head to read/write head of host disk drive | Jan 20, 1994 | Issued |
Array
(
[id] => 3439142
[patent_doc_number] => 05404564
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-04-04
[patent_title] => 'High speed data train generating system with no restriction on length of generated data train'
[patent_app_type] => 1
[patent_app_number] => 8/184856
[patent_app_country] => US
[patent_app_date] => 1994-01-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2717
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/404/05404564.pdf
[firstpage_image] =>[orig_patent_app_number] => 184856
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/184856 | High speed data train generating system with no restriction on length of generated data train | Jan 20, 1994 | Issued |
Array
(
[id] => 3553450
[patent_doc_number] => 05481744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-01-02
[patent_title] => 'Microcode sequencer changing states in response to an external gating input level change upon the occurrence of a wait instruction'
[patent_app_type] => 1
[patent_app_number] => 8/147552
[patent_app_country] => US
[patent_app_date] => 1993-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7595
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/481/05481744.pdf
[firstpage_image] =>[orig_patent_app_number] => 147552
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/147552 | Microcode sequencer changing states in response to an external gating input level change upon the occurrence of a wait instruction | Nov 4, 1993 | Issued |
Array
(
[id] => 3465972
[patent_doc_number] => 05379443
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-03
[patent_title] => 'Microprocessor providing encoded information on byte enable lines indicating whether reading code or data, location of code/data on data lines, and bit width of code/data'
[patent_app_type] => 1
[patent_app_number] => 8/133771
[patent_app_country] => US
[patent_app_date] => 1993-10-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2553
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 288
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/379/05379443.pdf
[firstpage_image] =>[orig_patent_app_number] => 133771
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/133771 | Microprocessor providing encoded information on byte enable lines indicating whether reading code or data, location of code/data on data lines, and bit width of code/data | Oct 7, 1993 | Issued |
Array
(
[id] => 3035775
[patent_doc_number] => 05327571
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-05
[patent_title] => 'Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right'
[patent_app_type] => 1
[patent_app_number] => 8/104398
[patent_app_country] => US
[patent_app_date] => 1993-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3583
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/327/05327571.pdf
[firstpage_image] =>[orig_patent_app_number] => 104398
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/104398 | Processor having decoder for decoding unmodified instruction set for addressing register to read or write in parallel or serially shift in from left or right | Aug 9, 1993 | Issued |
Array
(
[id] => 3505990
[patent_doc_number] => 05537590
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Apparatus for applying analysis rules to data sets in a relational database to generate a database of diagnostic records linked to the data sets'
[patent_app_type] => 1
[patent_app_number] => 8/102581
[patent_app_country] => US
[patent_app_date] => 1993-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 43
[patent_figures_cnt] => 93
[patent_no_of_words] => 27639
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 480
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/537/05537590.pdf
[firstpage_image] =>[orig_patent_app_number] => 102581
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/102581 | Apparatus for applying analysis rules to data sets in a relational database to generate a database of diagnostic records linked to the data sets | Aug 4, 1993 | Issued |