Search

Larry T. Mackall

Examiner (ID: 10850, Phone: (571)270-1172 , Office: P/2131 )

Most Active Art Unit
2139
Art Unit(s)
2131, 2139, 2189
Total Applications
904
Issued Applications
724
Pending Applications
65
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10991306 [patent_doc_number] => 20160188250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-30 [patent_title] => 'SORT OPERATION IN MEMORY' [patent_app_type] => utility [patent_app_number] => 14/920537 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 44082 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920537 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920537
Sort operation in memory Oct 21, 2015 Issued
Array ( [id] => 10778496 [patent_doc_number] => 20160124651 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'METHOD FOR PERFORMING RANDOM READ ACCESS TO A BLOCK OF DATA USING PARALLEL LUT READ INSTRUCTION IN VECTOR PROCESSORS' [patent_app_type] => utility [patent_app_number] => 14/920365 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920365 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920365
METHOD FOR PERFORMING RANDOM READ ACCESS TO A BLOCK OF DATA USING PARALLEL LUT READ INSTRUCTION IN VECTOR PROCESSORS Oct 21, 2015 Abandoned
Array ( [id] => 11591479 [patent_doc_number] => 20170115890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'ELIMINATING GARBAGE COLLECTION IN NAND FLASH DEVICES' [patent_app_type] => utility [patent_app_number] => 14/920617 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920617 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920617
Eliminating garbage collection in nand flash devices Oct 21, 2015 Issued
Array ( [id] => 11591720 [patent_doc_number] => 20170116131 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'DIVISION OF DATA STORAGE IN SINGLE-STORAGE DEVICE ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 14/920834 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5515 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920834 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920834
Division of data storage in single-storage device architecture Oct 21, 2015 Issued
Array ( [id] => 12248985 [patent_doc_number] => 09921759 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Multithreaded memory manager to de-allocate memory objects using private freelists' [patent_app_type] => utility [patent_app_number] => 14/920292 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920292 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/920292
Multithreaded memory manager to de-allocate memory objects using private freelists Oct 21, 2015 Issued
Array ( [id] => 10757465 [patent_doc_number] => 20160103617 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-14 [patent_title] => 'SYSTEM AND METHOD FOR DYNAMICALLY ADJUSTING GARBAGE COLLECTION POLICIES IN SOLID-STATE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/881103 [patent_app_country] => US [patent_app_date] => 2015-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4980 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14881103 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/881103
System and method for dynamically adjusting garbage collection policies in solid-state memory Oct 11, 2015 Issued
Array ( [id] => 13172001 [patent_doc_number] => 10102116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Multi-level page data structure [patent_app_type] => utility [patent_app_number] => 14/851166 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9619 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851166 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/851166
Multi-level page data structure Sep 10, 2015 Issued
Array ( [id] => 13187625 [patent_doc_number] => 10109338 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Semiconductor devices and semiconductor systems generating internal address [patent_app_type] => utility [patent_app_number] => 14/851275 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4495 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851275 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/851275
Semiconductor devices and semiconductor systems generating internal address Sep 10, 2015 Issued
Array ( [id] => 13664731 [patent_doc_number] => 10162525 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-25 [patent_title] => Translating access requests for a multi-level page data structure [patent_app_type] => utility [patent_app_number] => 14/851426 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9583 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851426 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/851426
Translating access requests for a multi-level page data structure Sep 10, 2015 Issued
Array ( [id] => 11501386 [patent_doc_number] => 20170075571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'MEMORY DEVICE AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/851208 [patent_app_country] => US [patent_app_date] => 2015-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8486 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14851208 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/851208
MEMORY DEVICE AND CONTROL METHOD THEREOF Sep 10, 2015 Abandoned
Array ( [id] => 11501434 [patent_doc_number] => 20170075619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'METHODS AND SYSTEMS TO DETECT SILENT CORRUPTION OF DATA' [patent_app_type] => utility [patent_app_number] => 14/850680 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6312 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850680 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/850680
Methods and systems to detect silent corruption of data Sep 9, 2015 Issued
Array ( [id] => 11501385 [patent_doc_number] => 20170075570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'REDUCING READ COMMAND LATENCY IN STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 14/850524 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3709 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850524 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/850524
Reducing read command latency in storage devices Sep 9, 2015 Issued
Array ( [id] => 12551397 [patent_doc_number] => 10013348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Parallel memory allocator employing liveness metrics [patent_app_type] => utility [patent_app_number] => 14/850474 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 11237 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850474 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/850474
Parallel memory allocator employing liveness metrics Sep 9, 2015 Issued
Array ( [id] => 13054975 [patent_doc_number] => 10048876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Method for providing nonvolatile storage write bandwidth using a caching namespace [patent_app_type] => utility [patent_app_number] => 14/850802 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5937 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850802 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/850802
Method for providing nonvolatile storage write bandwidth using a caching namespace Sep 9, 2015 Issued
Array ( [id] => 13185661 [patent_doc_number] => 10108350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Method for providing nonvolatile storage write bandwidth using a caching namespace [patent_app_type] => utility [patent_app_number] => 14/850741 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850741 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/850741
Method for providing nonvolatile storage write bandwidth using a caching namespace Sep 9, 2015 Issued
Array ( [id] => 10745963 [patent_doc_number] => 20160092114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'TECHNIQUES FOR SELECTING AMOUNTS OF OVER-PROVISIONING' [patent_app_type] => utility [patent_app_number] => 14/850587 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5069 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850587 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/850587
Techniques for selecting amounts of over-provisioning Sep 9, 2015 Issued
Array ( [id] => 11320839 [patent_doc_number] => 09519582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-13 [patent_title] => 'Sense operation flags in a memory device' [patent_app_type] => utility [patent_app_number] => 14/833175 [patent_app_country] => US [patent_app_date] => 2015-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3675 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14833175 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/833175
Sense operation flags in a memory device Aug 23, 2015 Issued
Array ( [id] => 11926323 [patent_doc_number] => 09793918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Memory compression operable for non-contiguous write/read addresses' [patent_app_type] => utility [patent_app_number] => 14/814617 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 10294 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14814617 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/814617
Memory compression operable for non-contiguous write/read addresses Jul 30, 2015 Abandoned
Array ( [id] => 14766527 [patent_doc_number] => 10394660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-27 [patent_title] => Snapshot restore workflow [patent_app_type] => utility [patent_app_number] => 14/815064 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13228 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14815064 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/815064
Snapshot restore workflow Jul 30, 2015 Issued
Array ( [id] => 11423479 [patent_doc_number] => 20170031622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-02 [patent_title] => 'METHODS FOR ALLOCATING STORAGE CLUSTER HARDWARE RESOURCES AND DEVICES THEREOF' [patent_app_type] => utility [patent_app_number] => 14/814668 [patent_app_country] => US [patent_app_date] => 2015-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6783 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14814668 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/814668
METHODS FOR ALLOCATING STORAGE CLUSTER HARDWARE RESOURCES AND DEVICES THEREOF Jul 30, 2015 Abandoned
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