Search

Larry T. Mackall

Examiner (ID: 10850, Phone: (571)270-1172 , Office: P/2131 )

Most Active Art Unit
2139
Art Unit(s)
2131, 2139, 2189
Total Applications
904
Issued Applications
724
Pending Applications
65
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19382965 [patent_doc_number] => 20240272835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => Remote Direct Memory Access in Multi-Tier Memory Systems [patent_app_type] => utility [patent_app_number] => 18/645761 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645761 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645761
Remote Direct Memory Access in Multi-Tier Memory Systems Apr 24, 2024 Pending
Array ( [id] => 20374028 [patent_doc_number] => 12481462 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Memory system and method of controlling nonvolatile memory with checking a total size indicative of a sum of data length specified by a write command [patent_app_type] => utility [patent_app_number] => 18/645482 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7598 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645482 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645482
Memory system and method of controlling nonvolatile memory with checking a total size indicative of a sum of data length specified by a write command Apr 24, 2024 Issued
Array ( [id] => 20731718 [patent_doc_number] => 12638976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Managed non-volatile memory device with data verification [patent_app_type] => utility [patent_app_number] => 18/644821 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10694 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18644821 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/644821
Managed non-volatile memory device with data verification Apr 23, 2024 Issued
Array ( [id] => 20174749 [patent_doc_number] => 12393496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => Techniques for accelerated data recovery [patent_app_type] => utility [patent_app_number] => 18/643781 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9481 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643781 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/643781
Techniques for accelerated data recovery Apr 22, 2024 Issued
Array ( [id] => 19362742 [patent_doc_number] => 20240264776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY AND FOR REDUCING A BUFFER SIZE [patent_app_type] => utility [patent_app_number] => 18/637512 [patent_app_country] => US [patent_app_date] => 2024-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637512 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637512
Memory system and method of controlling nonvolatile memory and for reducing a buffer size Apr 16, 2024 Issued
Array ( [id] => 19530102 [patent_doc_number] => 20240354004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => MULTITENANCY SSD CONFIGURATION [patent_app_type] => utility [patent_app_number] => 18/634873 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32141 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634873 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634873
MULTITENANCY SSD CONFIGURATION Apr 11, 2024 Pending
Array ( [id] => 19848732 [patent_doc_number] => 20250094083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => STORAGE DEVICE AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/634541 [patent_app_country] => US [patent_app_date] => 2024-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18634541 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/634541
STORAGE DEVICE AND METHOD OF OPERATING THE SAME Apr 11, 2024 Pending
Array ( [id] => 20159936 [patent_doc_number] => 12386562 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-12 [patent_title] => Dynamic status registers array [patent_app_type] => utility [patent_app_number] => 18/633028 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9567 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18633028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/633028
Dynamic status registers array Apr 10, 2024 Issued
Array ( [id] => 20745488 [patent_doc_number] => 12645400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Information processing system controlling first and second memory devices [patent_app_type] => utility [patent_app_number] => 18/630146 [patent_app_country] => US [patent_app_date] => 2024-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 5758 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18630146 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/630146
Information processing system controlling first and second memory devices Apr 8, 2024 Issued
Array ( [id] => 19514046 [patent_doc_number] => 20240345732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => DETECTION AND LATENCY REDUCTION OF WRITE-INTENSIVE PROCEDURES IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/625007 [patent_app_country] => US [patent_app_date] => 2024-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625007 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625007
DETECTION AND LATENCY REDUCTION OF WRITE-INTENSIVE PROCEDURES IN A MEMORY SYSTEM Apr 1, 2024 Pending
Array ( [id] => 19334216 [patent_doc_number] => 20240248646 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-25 [patent_title] => WORKLOAD-BASED SCAN OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/623881 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623881 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623881
Workload-based scan optimization Mar 31, 2024 Issued
Array ( [id] => 19857289 [patent_doc_number] => 12260126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => SSD managed host write atomicity with arbitrary transfer length [patent_app_type] => utility [patent_app_number] => 18/618532 [patent_app_country] => US [patent_app_date] => 2024-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8953 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18618532 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/618532
SSD managed host write atomicity with arbitrary transfer length Mar 26, 2024 Issued
Array ( [id] => 19514041 [patent_doc_number] => 20240345727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => DATA COMPRESSION FOR MAPPING TABLES [patent_app_type] => utility [patent_app_number] => 18/610028 [patent_app_country] => US [patent_app_date] => 2024-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12309 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610028 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610028
Data compression for mapping tables Mar 18, 2024 Issued
Array ( [id] => 20731714 [patent_doc_number] => 12638972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Analog computing configured memory [patent_app_type] => utility [patent_app_number] => 18/607266 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7037 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607266 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/607266
Analog computing configured memory Mar 14, 2024 Issued
Array ( [id] => 19603098 [patent_doc_number] => 20240393978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MEMORY DEVICE BACKGROUND OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/603746 [patent_app_country] => US [patent_app_date] => 2024-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6722 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603746 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603746
Memory device background operations Mar 12, 2024 Issued
Array ( [id] => 20234171 [patent_doc_number] => 20250291490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => ENHANCING READ PERFORMANCE OF A STORAGE DEVICE IN A MULTI-APPLICATION ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 18/603161 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603161 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603161
ENHANCING READ PERFORMANCE OF A STORAGE DEVICE IN A MULTI-APPLICATION ENVIRONMENT Mar 11, 2024 Pending
Array ( [id] => 20221466 [patent_doc_number] => 20250284397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-11 [patent_title] => PROCESSING WRITE OPERATION INFORMATION USING INFLATED DATA [patent_app_type] => utility [patent_app_number] => 18/598336 [patent_app_country] => US [patent_app_date] => 2024-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2237 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18598336 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/598336
Processing write operation information using inflated data Mar 6, 2024 Issued
Array ( [id] => 19419839 [patent_doc_number] => 20240295962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => PERFORMANCE MANANGEMENT USING INTELLIGENT PRIORITIZATION OF MEMORY OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/593678 [patent_app_country] => US [patent_app_date] => 2024-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593678 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/593678
Performance management using intelligent prioritization of memory operations Feb 29, 2024 Issued
Array ( [id] => 19382962 [patent_doc_number] => 20240272832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => ADAPTIVE BLOCK MAPPING [patent_app_type] => utility [patent_app_number] => 18/586207 [patent_app_country] => US [patent_app_date] => 2024-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19021 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18586207 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/586207
Adaptive block mapping Feb 22, 2024 Issued
Array ( [id] => 20195519 [patent_doc_number] => 20250272229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-28 [patent_title] => MEMORY SYSTEM WITH DYNAMICALLY ENUMERATED IDENTIFIERS [patent_app_type] => utility [patent_app_number] => 18/583942 [patent_app_country] => US [patent_app_date] => 2024-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5420 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18583942 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/583942
MEMORY SYSTEM WITH DYNAMICALLY ENUMERATED IDENTIFIERS Feb 21, 2024 Issued
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