Search

Larry T. Mackall

Examiner (ID: 10850, Phone: (571)270-1172 , Office: P/2131 )

Most Active Art Unit
2139
Art Unit(s)
2131, 2139, 2189
Total Applications
904
Issued Applications
724
Pending Applications
65
Abandoned Applications
134

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8823731 [patent_doc_number] => 20130124776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'SECURE DATA STORAGE IN RAID MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/296334 [patent_app_country] => US [patent_app_date] => 2011-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9840 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13296334 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/296334
Method and system for storing data in raid memory devices Nov 14, 2011 Issued
Array ( [id] => 8176576 [patent_doc_number] => 20120110296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/280614 [patent_app_country] => US [patent_app_date] => 2011-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5599 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20120110296.pdf [firstpage_image] =>[orig_patent_app_number] => 13280614 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/280614
Electronic apparatus with storage media having real address designated by stimulated request format and storage media having real address not designated by stimulated request format Oct 24, 2011 Issued
Array ( [id] => 8781929 [patent_doc_number] => 20130103904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'SYSTEM AND METHOD TO REDUCE MEMORY ACCESS LATENCIES USING SELECTIVE REPLICATION ACROSS MULTIPLE MEMORY PORTS' [patent_app_type] => utility [patent_app_number] => 13/280738 [patent_app_country] => US [patent_app_date] => 2011-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8333 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13280738 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/280738
System and method to reduce memory access latencies using selective replication across multiple memory ports Oct 24, 2011 Issued
Array ( [id] => 8781914 [patent_doc_number] => 20130103889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'PAGE-BUFFER MANAGEMENT OF NON-VOLATILE MEMORY-BASED MASS STORAGE DEVICES' [patent_app_type] => utility [patent_app_number] => 13/280597 [patent_app_country] => US [patent_app_date] => 2011-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5443 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13280597 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/280597
PAGE-BUFFER MANAGEMENT OF NON-VOLATILE MEMORY-BASED MASS STORAGE DEVICES Oct 24, 2011 Abandoned
Array ( [id] => 8781943 [patent_doc_number] => 20130103918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'Adaptive Concentrating Data Transmission Heap Buffer and Method' [patent_app_type] => utility [patent_app_number] => 13/280268 [patent_app_country] => US [patent_app_date] => 2011-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3513 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13280268 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/280268
Adaptive Concentrating Data Transmission Heap Buffer and Method Oct 23, 2011 Abandoned
Array ( [id] => 8574668 [patent_doc_number] => 08341329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine' [patent_app_type] => utility [patent_app_number] => 13/242070 [patent_app_country] => US [patent_app_date] => 2011-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5348 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13242070 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/242070
Method and system for providing hardware support for memory protection and virtual memory address translation for a virtual machine Sep 22, 2011 Issued
Array ( [id] => 8319647 [patent_doc_number] => 08234440 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Nonvolatile semiconductor memory device with advanced multi-page program operation' [patent_app_type] => utility [patent_app_number] => 13/239494 [patent_app_country] => US [patent_app_date] => 2011-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3937 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13239494 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/239494
Nonvolatile semiconductor memory device with advanced multi-page program operation Sep 21, 2011 Issued
Array ( [id] => 9980391 [patent_doc_number] => 09026722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Storing/reading several data streams into/from an array of memories' [patent_app_type] => utility [patent_app_number] => 13/816250 [patent_app_country] => US [patent_app_date] => 2011-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4182 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13816250 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/816250
Storing/reading several data streams into/from an array of memories Aug 7, 2011 Issued
Array ( [id] => 10034389 [patent_doc_number] => 09075708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-07-07 [patent_title] => 'System and method for improving data integrity and power-on performance in storage devices' [patent_app_type] => utility [patent_app_number] => 13/173431 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3864 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 296 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173431 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173431
System and method for improving data integrity and power-on performance in storage devices Jun 29, 2011 Issued
Array ( [id] => 10556088 [patent_doc_number] => 09280289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-08 [patent_title] => 'Detecting misalignment of virtualized data' [patent_app_type] => utility [patent_app_number] => 13/173452 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10366 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173452 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173452
Detecting misalignment of virtualized data Jun 29, 2011 Issued
Array ( [id] => 10125030 [patent_doc_number] => 09159396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-13 [patent_title] => 'Mechanism for facilitating fine-grained self-refresh control for dynamic memory devices' [patent_app_type] => utility [patent_app_number] => 13/173302 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7694 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173302 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173302
Mechanism for facilitating fine-grained self-refresh control for dynamic memory devices Jun 29, 2011 Issued
Array ( [id] => 8588589 [patent_doc_number] => 20130007410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'MULTIPATH STORAGE SYSTEM AND METHOD OF OPERATING THEREOF' [patent_app_type] => utility [patent_app_number] => 13/173465 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5147 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173465 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173465
Multipath storage system and method of operating thereof Jun 29, 2011 Issued
Array ( [id] => 7714077 [patent_doc_number] => 20120005400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'Dual In Line Memory Module with Multiple Memory Interfaces' [patent_app_type] => utility [patent_app_number] => 13/173450 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2188 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005400.pdf [firstpage_image] =>[orig_patent_app_number] => 13173450 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173450
Dual in line memory module with multiple memory interfaces Jun 29, 2011 Issued
Array ( [id] => 8588535 [patent_doc_number] => 20130007356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'Assigning A Classification To A Dual In-line Memory Module (DIMM)' [patent_app_type] => utility [patent_app_number] => 13/173404 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173404 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173404
Assigning A Classification To A Dual In-line Memory Module (DIMM) Jun 29, 2011 Abandoned
Array ( [id] => 13974393 [patent_doc_number] => 10216553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Message oriented middleware with integrated rules engine [patent_app_type] => utility [patent_app_number] => 13/173052 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3129 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173052 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173052
Message oriented middleware with integrated rules engine Jun 29, 2011 Issued
Array ( [id] => 10124311 [patent_doc_number] => 09158670 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-10-13 [patent_title] => 'System and method for dynamically adjusting garbage collection policies in solid-state memory' [patent_app_type] => utility [patent_app_number] => 13/173266 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4916 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173266 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173266
System and method for dynamically adjusting garbage collection policies in solid-state memory Jun 29, 2011 Issued
Array ( [id] => 8588552 [patent_doc_number] => 20130007373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'REGION BASED CACHE REPLACEMENT POLICY UTILIZING USAGE INFORMATION' [patent_app_type] => utility [patent_app_number] => 13/173441 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173441 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173441
REGION BASED CACHE REPLACEMENT POLICY UTILIZING USAGE INFORMATION Jun 29, 2011 Abandoned
Array ( [id] => 7809013 [patent_doc_number] => 20120059967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-08 [patent_title] => 'MEMORY BUS ARCHITECTURE FOR CONCURRENTLY SUPPORTING VOLATILE AND NON-VOLATILE MEMORY MODULES' [patent_app_type] => utility [patent_app_number] => 13/082312 [patent_app_country] => US [patent_app_date] => 2011-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 13368 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20120059967.pdf [firstpage_image] =>[orig_patent_app_number] => 13082312 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/082312
Memory bus architecture for concurrently supporting volatile and non-volatile memory modules Apr 6, 2011 Issued
Array ( [id] => 9077393 [patent_doc_number] => 08554985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Memory block identified by group of logical block addresses, storage device with movable sectors, and methods' [patent_app_type] => utility [patent_app_number] => 13/045159 [patent_app_country] => US [patent_app_date] => 2011-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 10806 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13045159 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/045159
Memory block identified by group of logical block addresses, storage device with movable sectors, and methods Mar 9, 2011 Issued
Array ( [id] => 8162553 [patent_doc_number] => 20120102274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'MEMORY MANAGING APPARATUS, MULTIPROCESSOR SYSTEM, AND METHOD FOR CAUSING MEMORY MANAGING APPARATUS TO MANAGE SHARED MEMORY' [patent_app_type] => utility [patent_app_number] => 13/027482 [patent_app_country] => US [patent_app_date] => 2011-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 5418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20120102274.pdf [firstpage_image] =>[orig_patent_app_number] => 13027482 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/027482
Processor, multiprocessor system, and method for causing memory managing apparatus to manage shared memory Feb 14, 2011 Issued
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