Search

Lars A. Olson

Examiner (ID: 5853, Phone: (571)272-6685 , Office: P/3617 )

Most Active Art Unit
3617
Art Unit(s)
3617, 3615
Total Applications
3322
Issued Applications
2755
Pending Applications
170
Abandoned Applications
427

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10378553 [patent_doc_number] => 20150263560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-17 [patent_title] => 'DISCHARGING CONTROL SYSTEM OF VEHICLE, DISCHARGING CONNECTOR, VEHICLE, AND DISCHARGING CONTROL METHOD OF VEHICLE' [patent_app_type] => utility [patent_app_number] => 14/416419 [patent_app_country] => US [patent_app_date] => 2013-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 13044 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14416419 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/416419
Discharging control system of vehicle, discharging connector, vehicle, and discharging control method of vehicle Oct 22, 2013 Issued
Array ( [id] => 10040592 [patent_doc_number] => 09081293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'System and method for lithography exposure with correction of overlay shift induced by mask heating' [patent_app_type] => utility [patent_app_number] => 14/056576 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5387 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056576 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056576
System and method for lithography exposure with correction of overlay shift induced by mask heating Oct 16, 2013 Issued
Array ( [id] => 9424380 [patent_doc_number] => 20140109031 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'CONFIGURATION OF SELECTED MODULES OF A HARDWARE BLOCK WITHIN A PROGRAMMABLE LOGIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/053026 [patent_app_country] => US [patent_app_date] => 2013-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3601 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14053026 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/053026
Configuration of selected modules of a hardware block within a programmable logic device Oct 13, 2013 Issued
Array ( [id] => 9826148 [patent_doc_number] => 08935645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-13 [patent_title] => 'Reconfigurable logic block' [patent_app_type] => utility [patent_app_number] => 14/048888 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8060 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14048888 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/048888
Reconfigurable logic block Oct 7, 2013 Issued
Array ( [id] => 10860898 [patent_doc_number] => 08887117 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-11 [patent_title] => 'Register clustering for clock network topology generation' [patent_app_type] => utility [patent_app_number] => 14/047296 [patent_app_country] => US [patent_app_date] => 2013-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6287 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14047296 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/047296
Register clustering for clock network topology generation Oct 6, 2013 Issued
Array ( [id] => 10184112 [patent_doc_number] => 09213793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-15 [patent_title] => 'Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks' [patent_app_type] => utility [patent_app_number] => 14/044836 [patent_app_country] => US [patent_app_date] => 2013-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 16484 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14044836 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/044836
Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracks Oct 1, 2013 Issued
Array ( [id] => 10873381 [patent_doc_number] => 08898602 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Apparatus for design assist and method for selecting signal line onto which test point for test controlling is to be inserted in circuit to be designed' [patent_app_type] => utility [patent_app_number] => 14/034616 [patent_app_country] => US [patent_app_date] => 2013-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 25 [patent_no_of_words] => 11984 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14034616 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/034616
Apparatus for design assist and method for selecting signal line onto which test point for test controlling is to be inserted in circuit to be designed Sep 23, 2013 Issued
Array ( [id] => 10157798 [patent_doc_number] => 09189580 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-17 [patent_title] => 'Analysis of stress impact on transistor performance' [patent_app_type] => utility [patent_app_number] => 14/025600 [patent_app_country] => US [patent_app_date] => 2013-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6017 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14025600 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/025600
Analysis of stress impact on transistor performance Sep 11, 2013 Issued
Array ( [id] => 9225154 [patent_doc_number] => 20140019929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'Partial Instruction-by-instruction checking on acceleration platforms' [patent_app_type] => utility [patent_app_number] => 14/016141 [patent_app_country] => US [patent_app_date] => 2013-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6957 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016141 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016141
Partial Instruction-by-instruction checking on acceleration platforms Sep 1, 2013 Abandoned
Array ( [id] => 9912431 [patent_doc_number] => 20150067634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'METHOD FOR POWER ESTIMATION FOR VIRTUAL PROTOTYPING MODELS FOR SEMICONDUCTORS' [patent_app_type] => utility [patent_app_number] => 14/016206 [patent_app_country] => US [patent_app_date] => 2013-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4897 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14016206 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/016206
Method for power estimation for virtual prototyping models for semiconductors Sep 1, 2013 Issued
Array ( [id] => 11230463 [patent_doc_number] => 09457682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-04 [patent_title] => 'Method for predicting charging process duration' [patent_app_type] => utility [patent_app_number] => 14/015120 [patent_app_country] => US [patent_app_date] => 2013-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 12619 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14015120 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/015120
Method for predicting charging process duration Aug 29, 2013 Issued
Array ( [id] => 9912421 [patent_doc_number] => 20150067624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'SYSTEM AND METHOD FOR LEAKAGE ESTIMATION FOR STANDARD INTEGRATED CIRCUIT CELLS WITH SHARED POLYCRYSTALLINE SILICON-ON-OXIDE DEFINITION-EDGE (PODE)' [patent_app_type] => utility [patent_app_number] => 14/015846 [patent_app_country] => US [patent_app_date] => 2013-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14015846 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/015846
System and method for leakage estimation for standard integrated circuit cells with shared polycrystalline silicon-on-oxide definition-edge (PODE) Aug 29, 2013 Issued
Array ( [id] => 10505758 [patent_doc_number] => 09233621 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Battery system and method for identifying unauthorized module replacement in a battery system' [patent_app_type] => utility [patent_app_number] => 14/010313 [patent_app_country] => US [patent_app_date] => 2013-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1710 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14010313 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/010313
Battery system and method for identifying unauthorized module replacement in a battery system Aug 25, 2013 Issued
Array ( [id] => 10566950 [patent_doc_number] => 09290104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-22 [patent_title] => 'Power control apparatus and methods for electric vehicles' [patent_app_type] => utility [patent_app_number] => 13/975313 [patent_app_country] => US [patent_app_date] => 2013-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 34 [patent_no_of_words] => 17196 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13975313 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/975313
Power control apparatus and methods for electric vehicles Aug 23, 2013 Issued
Array ( [id] => 11764519 [patent_doc_number] => 09372946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Defect injection for transistor-level fault simulation' [patent_app_type] => utility [patent_app_number] => 13/974006 [patent_app_country] => US [patent_app_date] => 2013-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6152 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13974006 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/974006
Defect injection for transistor-level fault simulation Aug 21, 2013 Issued
Array ( [id] => 11764519 [patent_doc_number] => 09372946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Defect injection for transistor-level fault simulation' [patent_app_type] => utility [patent_app_number] => 13/974006 [patent_app_country] => US [patent_app_date] => 2013-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6152 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13974006 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/974006
Defect injection for transistor-level fault simulation Aug 21, 2013 Issued
Array ( [id] => 11764519 [patent_doc_number] => 09372946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Defect injection for transistor-level fault simulation' [patent_app_type] => utility [patent_app_number] => 13/974006 [patent_app_country] => US [patent_app_date] => 2013-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6152 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13974006 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/974006
Defect injection for transistor-level fault simulation Aug 21, 2013 Issued
Array ( [id] => 11764519 [patent_doc_number] => 09372946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-21 [patent_title] => 'Defect injection for transistor-level fault simulation' [patent_app_type] => utility [patent_app_number] => 13/974006 [patent_app_country] => US [patent_app_date] => 2013-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 6152 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13974006 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/974006
Defect injection for transistor-level fault simulation Aug 21, 2013 Issued
Array ( [id] => 10907659 [patent_doc_number] => 20140310674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-16 [patent_title] => 'SYSTEM AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINE' [patent_app_type] => utility [patent_app_number] => 13/968386 [patent_app_country] => US [patent_app_date] => 2013-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 996 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13968386 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/968386
SYSTEM AND METHOD FOR CHECKING SIGNAL TRANSMISSION LINE Aug 14, 2013 Abandoned
Array ( [id] => 9688478 [patent_doc_number] => 20140245243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'COMPUTING DEVICE AND METHOD FOR GENERATING COMPONENT MODULE FILES OF CIRCUIT DIAGRAM' [patent_app_type] => utility [patent_app_number] => 13/965236 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1271 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965236 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/965236
COMPUTING DEVICE AND METHOD FOR GENERATING COMPONENT MODULE FILES OF CIRCUIT DIAGRAM Aug 12, 2013 Abandoned
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