Search

Lars A. Olson

Examiner (ID: 5853, Phone: (571)272-6685 , Office: P/3617 )

Most Active Art Unit
3617
Art Unit(s)
3617, 3615
Total Applications
3322
Issued Applications
2755
Pending Applications
170
Abandoned Applications
427

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9315082 [patent_doc_number] => 08656318 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'System and method for combined intraoverlay metrology and defect inspection' [patent_app_type] => utility [patent_app_number] => 13/464116 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4864 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13464116 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/464116
System and method for combined intraoverlay metrology and defect inspection May 3, 2012 Issued
Array ( [id] => 9444371 [patent_doc_number] => 08713507 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-29 [patent_title] => 'Method and apparatus for efficiently inserting fills in an integrated circuit layout' [patent_app_type] => utility [patent_app_number] => 13/463816 [patent_app_country] => US [patent_app_date] => 2012-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 15270 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13463816 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/463816
Method and apparatus for efficiently inserting fills in an integrated circuit layout May 3, 2012 Issued
Array ( [id] => 8657444 [patent_doc_number] => 20130038273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'CRITICAL MODE CONTROL DISCONTINUOUS MODE BOOST-BUCK CHARGER' [patent_app_type] => utility [patent_app_number] => 13/458710 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4770 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458710 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/458710
Critical mode control discontinuous mode boost-buck charger Apr 26, 2012 Issued
Array ( [id] => 8497941 [patent_doc_number] => 20120297349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'METHOD OF DESIGNING A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/458516 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7722 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458516 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/458516
Methods of designing semiconductor devices and methods of modifying layouts of semiconductor devices Apr 26, 2012 Issued
Array ( [id] => 8474872 [patent_doc_number] => 20120274279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-01 [patent_title] => 'BATTERY MANAGEMENT SYSTEM FOR CONTROL OF LITHIUM POWER CELLS' [patent_app_type] => utility [patent_app_number] => 13/458952 [patent_app_country] => US [patent_app_date] => 2012-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10538 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13458952 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/458952
Battery management system for control of lithium power cells Apr 26, 2012 Issued
Array ( [id] => 9500251 [patent_doc_number] => 08739092 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-05-27 [patent_title] => 'Functional property ranking' [patent_app_type] => utility [patent_app_number] => 13/455926 [patent_app_country] => US [patent_app_date] => 2012-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 9864 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13455926 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/455926
Functional property ranking Apr 24, 2012 Issued
Array ( [id] => 9083378 [patent_doc_number] => 20130268908 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'VIA SELECTION IN INTEGRATED CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 13/443426 [patent_app_country] => US [patent_app_date] => 2012-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4692 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13443426 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/443426
Via selection in integrated circuit design Apr 9, 2012 Issued
Array ( [id] => 9367895 [patent_doc_number] => 20140077768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'COMMUNICATION METHOD, COMMUNICATION SYSTEM, AND ENERGY STORAGE SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/117612 [patent_app_country] => US [patent_app_date] => 2012-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9054 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14117612 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/117612
Communication method, communication system, and energy storage system including the same Mar 29, 2012 Issued
Array ( [id] => 9783493 [patent_doc_number] => 20140300313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'PROCESSING APPARATUS, CHARGING SYSTEM, CHARGING METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 14/117526 [patent_app_country] => US [patent_app_date] => 2012-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4853 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14117526 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/117526
PROCESSING APPARATUS, CHARGING SYSTEM, CHARGING METHOD, AND PROGRAM Mar 22, 2012 Abandoned
Array ( [id] => 9248616 [patent_doc_number] => 08612918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Method for extracting information for a circuit design' [patent_app_type] => utility [patent_app_number] => 13/427486 [patent_app_country] => US [patent_app_date] => 2012-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10676 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13427486 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/427486
Method for extracting information for a circuit design Mar 21, 2012 Issued
Array ( [id] => 8935803 [patent_doc_number] => 08495525 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-23 [patent_title] => 'Lithographic error reduction by pattern matching' [patent_app_type] => utility [patent_app_number] => 13/424816 [patent_app_country] => US [patent_app_date] => 2012-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5525 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424816 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/424816
Lithographic error reduction by pattern matching Mar 19, 2012 Issued
Array ( [id] => 8287356 [patent_doc_number] => 20120175683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-12 [patent_title] => 'Basic Cell Architecture For Structured ASICs' [patent_app_type] => utility [patent_app_number] => 13/424747 [patent_app_country] => US [patent_app_date] => 2012-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7773 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13424747 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/424747
Basic cell architecture for structured ASICs Mar 19, 2012 Issued
Array ( [id] => 8325996 [patent_doc_number] => 20120198406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS' [patent_app_type] => utility [patent_app_number] => 13/422566 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9387 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422566 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/422566
UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS Mar 15, 2012 Abandoned
Array ( [id] => 8315114 [patent_doc_number] => 20120192136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'ORDERING OF STATISTICAL CORRELATED QUANTITIES' [patent_app_type] => utility [patent_app_number] => 13/422637 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422637 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/422637
Ordering of statistical correlated quantities Mar 15, 2012 Issued
Array ( [id] => 8325996 [patent_doc_number] => 20120198406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS' [patent_app_type] => utility [patent_app_number] => 13/422566 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9387 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422566 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/422566
UNIVERSAL INTER-LAYER INTERCONNECT FOR MULTI-LAYER SEMICONDUCTOR STACKS Mar 15, 2012 Abandoned
Array ( [id] => 8722810 [patent_doc_number] => 20130074027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-21 [patent_title] => 'DESIGNING DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/422236 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5864 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422236 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/422236
DESIGNING DEVICE FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND DESIGNING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT Mar 15, 2012 Abandoned
Array ( [id] => 8315114 [patent_doc_number] => 20120192136 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'ORDERING OF STATISTICAL CORRELATED QUANTITIES' [patent_app_type] => utility [patent_app_number] => 13/422637 [patent_app_country] => US [patent_app_date] => 2012-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13422637 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/422637
Ordering of statistical correlated quantities Mar 15, 2012 Issued
Array ( [id] => 9049391 [patent_doc_number] => 08543949 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-24 [patent_title] => 'Allocating hardware resources for high-level language code sequences' [patent_app_type] => utility [patent_app_number] => 13/421410 [patent_app_country] => US [patent_app_date] => 2012-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6552 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13421410 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/421410
Allocating hardware resources for high-level language code sequences Mar 14, 2012 Issued
Array ( [id] => 9195704 [patent_doc_number] => 20130335019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'ELECTRONIC EQUIPMENT AND CHARGING METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 14/001721 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3605 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14001721 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/001721
ELECTRONIC EQUIPMENT AND CHARGING METHOD THEREFOR Mar 12, 2012 Abandoned
Array ( [id] => 8280178 [patent_doc_number] => 20120174053 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'TEMPORALLY-ASSISTED RESOURCE SHARING IN ELECTRONIC SYSTEMS' [patent_app_type] => utility [patent_app_number] => 13/417062 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 18194 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13417062 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/417062
Temporally-assisted resource sharing in electronic systems Mar 8, 2012 Issued
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