Search

Lars A. Olson

Examiner (ID: 5853, Phone: (571)272-6685 , Office: P/3617 )

Most Active Art Unit
3617
Art Unit(s)
3617, 3615
Total Applications
3322
Issued Applications
2755
Pending Applications
170
Abandoned Applications
427

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9036442 [patent_doc_number] => 20130239080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-12 [patent_title] => 'HIERARCHICAL BOTTOM-UP CLOCK DOMAIN CROSSING VERIFICATION' [patent_app_type] => utility [patent_app_number] => 13/416856 [patent_app_country] => US [patent_app_date] => 2012-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4507 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13416856 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/416856
Hierarchical bottom-up clock domain crossing verification Mar 8, 2012 Issued
Array ( [id] => 9248622 [patent_doc_number] => 08612924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-17 [patent_title] => 'Support program, support apparatus, and support method to change a display attribute of a component in a displayed circuit' [patent_app_type] => utility [patent_app_number] => 13/414136 [patent_app_country] => US [patent_app_date] => 2012-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6853 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13414136 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/414136
Support program, support apparatus, and support method to change a display attribute of a component in a displayed circuit Mar 6, 2012 Issued
Array ( [id] => 10182131 [patent_doc_number] => 09211801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-15 [patent_title] => 'Charging cable for electrically-driven vehicle' [patent_app_type] => utility [patent_app_number] => 14/001822 [patent_app_country] => US [patent_app_date] => 2012-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4616 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14001822 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/001822
Charging cable for electrically-driven vehicle Mar 1, 2012 Issued
Array ( [id] => 9689284 [patent_doc_number] => RE045110 [patent_country] => US [patent_kind] => E1 [patent_issue_date] => 2014-09-02 [patent_title] => 'MPGA products based on a prototype FPGA' [patent_app_type] => reissue [patent_app_number] => 13/411486 [patent_app_country] => US [patent_app_date] => 2012-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 12405 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13411486 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/411486
MPGA products based on a prototype FPGA Mar 1, 2012 Issued
Array ( [id] => 8395737 [patent_doc_number] => 20120233574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM, DECISION METHOD AND COMPUTER' [patent_app_type] => utility [patent_app_number] => 13/409466 [patent_app_country] => US [patent_app_date] => 2012-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10881 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13409466 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/409466
Non-transitory computer-readable storage medium, decision method and computer for deciding exposure condition using evaluation item of interest and auxiliary evaluation item Feb 29, 2012 Issued
Array ( [id] => 9194962 [patent_doc_number] => 20130334277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'ELECTRIC TOOL AND METHOD OF DRIVING ELECTRIC TOOL' [patent_app_type] => utility [patent_app_number] => 14/001801 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10617 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14001801 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/001801
ELECTRIC TOOL AND METHOD OF DRIVING ELECTRIC TOOL Feb 27, 2012 Abandoned
Array ( [id] => 8395744 [patent_doc_number] => 20120233580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'TIMING VERIFICATION SUPPORT DEVICE, METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 13/406906 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 9439 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13406906 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406906
Timing verification support device generating second circuit data including circuit elements identified from first circuit data and timing verification support method Feb 27, 2012 Issued
Array ( [id] => 10873396 [patent_doc_number] => 08898617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Robust design using manufacturability models' [patent_app_type] => utility [patent_app_number] => 13/401693 [patent_app_country] => US [patent_app_date] => 2012-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 8290 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13401693 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/401693
Robust design using manufacturability models Feb 20, 2012 Issued
Array ( [id] => 9195719 [patent_doc_number] => 20130335034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'CHARGING METHOD FOR NON-AQUEOUS ELECTROLYTE SECONDARY BATTERY, AND BATTERY PACK' [patent_app_type] => utility [patent_app_number] => 14/001834 [patent_app_country] => US [patent_app_date] => 2012-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 12119 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14001834 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/001834
Charging method for non-aqueous electrolyte secondary battery, and battery pack Feb 19, 2012 Issued
Array ( [id] => 9029794 [patent_doc_number] => 08539392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-17 [patent_title] => 'Method for compensating proximity effects of particle beam lithography processes' [patent_app_type] => utility [patent_app_number] => 13/399096 [patent_app_country] => US [patent_app_date] => 2012-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1658 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13399096 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/399096
Method for compensating proximity effects of particle beam lithography processes Feb 16, 2012 Issued
Array ( [id] => 8979117 [patent_doc_number] => 20130212547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'METHOD OF EXTRACTING BLOCK BINDERS AND AN APPLICATION IN BLOCK PLACEMENT FOR AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/371616 [patent_app_country] => US [patent_app_date] => 2012-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8652 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13371616 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/371616
Method of extracting block binders and an application in block placement for an integrated circuit Feb 12, 2012 Issued
Array ( [id] => 8357141 [patent_doc_number] => 20120212299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-23 [patent_title] => 'METHOD FOR DETERMINING DESIGN VALUES FOR CRYSTAL OSCILLATOR CIRCUIT AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/370746 [patent_app_country] => US [patent_app_date] => 2012-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4702 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13370746 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/370746
METHOD FOR DETERMINING DESIGN VALUES FOR CRYSTAL OSCILLATOR CIRCUIT AND ELECTRONIC APPARATUS Feb 9, 2012 Abandoned
Array ( [id] => 9116346 [patent_doc_number] => 08572538 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Reconfigurable logic block' [patent_app_type] => utility [patent_app_number] => 13/369226 [patent_app_country] => US [patent_app_date] => 2012-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8035 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369226 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/369226
Reconfigurable logic block Feb 7, 2012 Issued
Array ( [id] => 9695564 [patent_doc_number] => 08826194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-02 [patent_title] => 'Pattern data generating apparatus' [patent_app_type] => utility [patent_app_number] => 13/368196 [patent_app_country] => US [patent_app_date] => 2012-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2456 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13368196 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/368196
Pattern data generating apparatus Feb 6, 2012 Issued
Array ( [id] => 8843493 [patent_doc_number] => 20130139121 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-30 [patent_title] => 'RC Extraction Methodology for Floating Silicon Substrate with TSV' [patent_app_type] => utility [patent_app_number] => 13/366756 [patent_app_country] => US [patent_app_date] => 2012-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13366756 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/366756
RC extraction methodology for floating silicon substrate with TSV Feb 5, 2012 Issued
Array ( [id] => 8878906 [patent_doc_number] => 08473891 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-25 [patent_title] => 'System and method for integrated circuit layout editing using reference frames' [patent_app_type] => utility [patent_app_number] => 13/362906 [patent_app_country] => US [patent_app_date] => 2012-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 17 [patent_no_of_words] => 11832 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13362906 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/362906
System and method for integrated circuit layout editing using reference frames Jan 30, 2012 Issued
Array ( [id] => 11218352 [patent_doc_number] => 09446676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Charging station for wired charging of electric vehicle' [patent_app_type] => utility [patent_app_number] => 13/983253 [patent_app_country] => US [patent_app_date] => 2012-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5515 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13983253 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/983253
Charging station for wired charging of electric vehicle Jan 29, 2012 Issued
Array ( [id] => 8325992 [patent_doc_number] => 20120198401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'APPARATUS AND METHOD OF SUPPORTING DESIGN OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/360246 [patent_app_country] => US [patent_app_date] => 2012-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4639 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13360246 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/360246
APPARATUS AND METHOD OF SUPPORTING DESIGN OF SEMICONDUCTOR DEVICE Jan 26, 2012 Abandoned
Array ( [id] => 8201012 [patent_doc_number] => 20120123763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'METHOD AND APPARATUS FOR EXECUTING A HARDWARE SIMULATION AND VERIFICATION SOLUTION' [patent_app_type] => utility [patent_app_number] => 13/359386 [patent_app_country] => US [patent_app_date] => 2012-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6699 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20120123763.pdf [firstpage_image] =>[orig_patent_app_number] => 13359386 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/359386
Method and apparatus for executing a hardware simulation and verification solution Jan 25, 2012 Issued
Array ( [id] => 8810447 [patent_doc_number] => 08448114 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-21 [patent_title] => 'Method for dual edge clock and buffer tree synthesis' [patent_app_type] => utility [patent_app_number] => 13/356636 [patent_app_country] => US [patent_app_date] => 2012-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2740 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13356636 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/356636
Method for dual edge clock and buffer tree synthesis Jan 22, 2012 Issued
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