
Lars A. Olson
Examiner (ID: 5853, Phone: (571)272-6685 , Office: P/3617 )
| Most Active Art Unit | 3617 |
| Art Unit(s) | 3617, 3615 |
| Total Applications | 3322 |
| Issued Applications | 2755 |
| Pending Applications | 170 |
| Abandoned Applications | 427 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8661385
[patent_doc_number] => 20130042214
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-02-14
[patent_title] => 'IIMPLEMENTING Z DIRECTIONAL MACRO PORT ASSIGNMENT'
[patent_app_type] => utility
[patent_app_number] => 13/208046
[patent_app_country] => US
[patent_app_date] => 2011-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 3382
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13208046
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/208046 | Implementing Z directional macro port assignment | Aug 10, 2011 | Issued |
Array
(
[id] => 8194992
[patent_doc_number] => 08185860
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-05-22
[patent_title] => 'Method for matching timing on high fanout signal paths using routing guides'
[patent_app_type] => utility
[patent_app_number] => 13/206449
[patent_app_country] => US
[patent_app_date] => 2011-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 5223
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/185/08185860.pdf
[firstpage_image] =>[orig_patent_app_number] => 13206449
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/206449 | Method for matching timing on high fanout signal paths using routing guides | Aug 8, 2011 | Issued |
Array
(
[id] => 8818901
[patent_doc_number] => 20130119947
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2013-05-16
[patent_title] => 'STORAGE BATTERY CONTROL DEVICE, CHARGING STATION, AND STORAGE BATTERY CONTROL METHOD'
[patent_app_type] => utility
[patent_app_number] => 13/810538
[patent_app_country] => US
[patent_app_date] => 2011-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 9552
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13810538
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/810538 | Storage battery control device, charging station, and storage battery control method | Jul 31, 2011 | Issued |
Array
(
[id] => 9023658
[patent_doc_number] => 08533657
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-10
[patent_title] => 'Printed circuit boards having pads for solder balls and methods for the implementation thereof'
[patent_app_type] => utility
[patent_app_number] => 13/195638
[patent_app_country] => US
[patent_app_date] => 2011-08-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4028
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13195638
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/195638 | Printed circuit boards having pads for solder balls and methods for the implementation thereof | Jul 31, 2011 | Issued |
Array
(
[id] => 8849425
[patent_doc_number] => 08458625
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-04
[patent_title] => 'Yield enhancement by multiplicate-layer-handling optical correction'
[patent_app_type] => utility
[patent_app_number] => 13/193716
[patent_app_country] => US
[patent_app_date] => 2011-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 5774
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 163
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193716
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/193716 | Yield enhancement by multiplicate-layer-handling optical correction | Jul 28, 2011 | Issued |
Array
(
[id] => 8959176
[patent_doc_number] => 08504970
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-08-06
[patent_title] => 'Method and apparatus for performing automated timing closure analysis for systems implemented on target devices'
[patent_app_type] => utility
[patent_app_number] => 13/176126
[patent_app_country] => US
[patent_app_date] => 2011-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 8446
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13176126
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/176126 | Method and apparatus for performing automated timing closure analysis for systems implemented on target devices | Jul 4, 2011 | Issued |
Array
(
[id] => 9029822
[patent_doc_number] => 08539420
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-09-17
[patent_title] => 'Method and apparatus for self-annealing multi-die interconnect redundancy control'
[patent_app_type] => utility
[patent_app_number] => 13/176586
[patent_app_country] => US
[patent_app_date] => 2011-07-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 33
[patent_no_of_words] => 12885
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13176586
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/176586 | Method and apparatus for self-annealing multi-die interconnect redundancy control | Jul 4, 2011 | Issued |
Array
(
[id] => 10029153
[patent_doc_number] => 09071068
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-06-30
[patent_title] => 'Charge/discharge control apparatus'
[patent_app_type] => utility
[patent_app_number] => 13/807910
[patent_app_country] => US
[patent_app_date] => 2011-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 6490
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13807910
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/807910 | Charge/discharge control apparatus | Jun 28, 2011 | Issued |
Array
(
[id] => 8728514
[patent_doc_number] => 08407656
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-03-26
[patent_title] => 'Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range'
[patent_app_type] => utility
[patent_app_number] => 13/167826
[patent_app_country] => US
[patent_app_date] => 2011-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 8813
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167826
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/167826 | Method and structure for a transistor having a relatively large threshold voltage variation range and for a random number generator incorporating multiple essentially identical transistors having such a large threshold voltage variation range | Jun 23, 2011 | Issued |
Array
(
[id] => 8752264
[patent_doc_number] => 08418108
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-09
[patent_title] => 'Accuracy pin-slew mode for gate delay calculation'
[patent_app_type] => utility
[patent_app_number] => 13/162806
[patent_app_country] => US
[patent_app_date] => 2011-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 5615
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162806
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/162806 | Accuracy pin-slew mode for gate delay calculation | Jun 16, 2011 | Issued |
Array
(
[id] => 8059413
[patent_doc_number] => 20120079438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-29
[patent_title] => 'INTEGRATED CIRCUIT DESIGN FRAMEWORK COMPRISING AUTOMATIC ANALYSIS FUNCTIONALITY'
[patent_app_type] => utility
[patent_app_number] => 13/158656
[patent_app_country] => US
[patent_app_date] => 2011-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7044
[patent_no_of_claims] => 43
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0079/20120079438.pdf
[firstpage_image] =>[orig_patent_app_number] => 13158656
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/158656 | Integrated circuit design framework comprising automatic analysis functionality | Jun 12, 2011 | Issued |
Array
(
[id] => 7658584
[patent_doc_number] => 20110307853
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-12-15
[patent_title] => 'METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE'
[patent_app_type] => utility
[patent_app_number] => 13/159116
[patent_app_country] => US
[patent_app_date] => 2011-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5904
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0307/20110307853.pdf
[firstpage_image] =>[orig_patent_app_number] => 13159116
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/159116 | METHOD OF DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE | Jun 12, 2011 | Abandoned |
Array
(
[id] => 10503015
[patent_doc_number] => 09231418
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-05
[patent_title] => 'Method for monitoring a charging process of a battery'
[patent_app_type] => utility
[patent_app_number] => 13/806108
[patent_app_country] => US
[patent_app_date] => 2011-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3281
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13806108
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/806108 | Method for monitoring a charging process of a battery | May 9, 2011 | Issued |
Array
(
[id] => 8438333
[patent_doc_number] => 08286118
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-10-09
[patent_title] => 'Integrated circuit devices and methods and apparatuses for designing integrated circuit devices'
[patent_app_type] => utility
[patent_app_number] => 13/101043
[patent_app_country] => US
[patent_app_date] => 2011-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 38
[patent_no_of_words] => 18102
[patent_no_of_claims] => 72
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13101043
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/101043 | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices | May 3, 2011 | Issued |
Array
(
[id] => 8479267
[patent_doc_number] => 20120278675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-11-01
[patent_title] => 'METHOD AND APPARATUS FOR PERFORMING IMPLICATION AND DECISION MAKING USING MULTIPLE VALUE SYSTEMS DURING CONSTRAINT SOLVING'
[patent_app_type] => utility
[patent_app_number] => 13/098136
[patent_app_country] => US
[patent_app_date] => 2011-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 6957
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13098136
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/098136 | Performing implication and decision making using multiple value systems during constraint solving | Apr 28, 2011 | Issued |
Array
(
[id] => 7820040
[patent_doc_number] => 20120066660
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-03-15
[patent_title] => 'METHOD OF MANAGING PROCESS FACTORS THAT INFLUENCE ELECTRICAL PROPERTIES OF PRINTED CIRCUIT BOARDS'
[patent_app_type] => utility
[patent_app_number] => 13/092966
[patent_app_country] => US
[patent_app_date] => 2011-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 2041
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0066/20120066660.pdf
[firstpage_image] =>[orig_patent_app_number] => 13092966
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/092966 | Method of managing process factors that influence electrical properties of printed circuit boards | Apr 23, 2011 | Issued |
Array
(
[id] => 8467027
[patent_doc_number] => 20120272195
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-10-25
[patent_title] => 'SYSTEM AND METHOD FOR OPTICAL PROXIMITY CORRECTION OF A MODIFIED INTEGRATED CIRCUIT LAYOUT'
[patent_app_type] => utility
[patent_app_number] => 13/091316
[patent_app_country] => US
[patent_app_date] => 2011-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 5218
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13091316
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/091316 | System and method for optical proximity correction of a modified integrated circuit layout | Apr 20, 2011 | Issued |
Array
(
[id] => 9236101
[patent_doc_number] => 08601417
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-12-03
[patent_title] => 'Decomposition based approach for the synthesis of threshold logic circuits'
[patent_app_type] => utility
[patent_app_number] => 13/090796
[patent_app_country] => US
[patent_app_date] => 2011-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 27
[patent_no_of_words] => 13317
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13090796
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/090796 | Decomposition based approach for the synthesis of threshold logic circuits | Apr 19, 2011 | Issued |
Array
(
[id] => 9202847
[patent_doc_number] => 20140002024
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-01-02
[patent_title] => 'ADAPTER AND VEHICLE FOR PERFORMING POWER FEEDING USING ADAPTER'
[patent_app_type] => utility
[patent_app_number] => 14/001734
[patent_app_country] => US
[patent_app_date] => 2011-03-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 10681
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14001734
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/001734 | Adapter and vehicle for performing power feeding using adapter | Mar 22, 2011 | Issued |
Array
(
[id] => 8623349
[patent_doc_number] => 08356271
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-01-15
[patent_title] => 'Layout testing method and wafer manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 13/050276
[patent_app_country] => US
[patent_app_date] => 2011-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4724
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 57
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13050276
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/050276 | Layout testing method and wafer manufacturing method | Mar 16, 2011 | Issued |