Search

Lars A. Olson

Examiner (ID: 5853, Phone: (571)272-6685 , Office: P/3617 )

Most Active Art Unit
3617
Art Unit(s)
3617, 3615
Total Applications
3322
Issued Applications
2755
Pending Applications
170
Abandoned Applications
427

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6167157 [patent_doc_number] => 20110161909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Methods for Designing Semiconductor Device with Dynamic Array Section' [patent_app_type] => utility [patent_app_number] => 13/047474 [patent_app_country] => US [patent_app_date] => 2011-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 76 [patent_figures_cnt] => 76 [patent_no_of_words] => 33288 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161909.pdf [firstpage_image] =>[orig_patent_app_number] => 13047474 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/047474
Methods for designing semiconductor device with dynamic array section Mar 13, 2011 Issued
Array ( [id] => 8775612 [patent_doc_number] => 08429588 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Method and mechanism for extraction and recognition of polygons in an IC design' [patent_app_type] => utility [patent_app_number] => 13/047685 [patent_app_country] => US [patent_app_date] => 2011-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5938 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13047685 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/047685
Method and mechanism for extraction and recognition of polygons in an IC design Mar 13, 2011 Issued
Array ( [id] => 10611450 [patent_doc_number] => 09331497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Electrical energy storage unit and control system and applications thereof' [patent_app_type] => utility [patent_app_number] => 13/978689 [patent_app_country] => US [patent_app_date] => 2011-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 40 [patent_no_of_words] => 15779 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13978689 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/978689
Electrical energy storage unit and control system and applications thereof Mar 4, 2011 Issued
Array ( [id] => 8716246 [patent_doc_number] => 08402400 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-19 [patent_title] => 'Method and apparatus for implementing a processor interface block with an electronic design automation tool' [patent_app_type] => utility [patent_app_number] => 12/932140 [patent_app_country] => US [patent_app_date] => 2011-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 12599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12932140 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/932140
Method and apparatus for implementing a processor interface block with an electronic design automation tool Feb 17, 2011 Issued
Array ( [id] => 6057685 [patent_doc_number] => 20110113400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'METHOD OF MAKING IN AN INTEGRATED CIRCUIT INCLUDING SIMPLIFYING METAL SHAPES' [patent_app_type] => utility [patent_app_number] => 13/010394 [patent_app_country] => US [patent_app_date] => 2011-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11374 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113400.pdf [firstpage_image] =>[orig_patent_app_number] => 13010394 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/010394
Method of making in an integrated circuit including simplifying metal shapes Jan 19, 2011 Issued
Array ( [id] => 9236113 [patent_doc_number] => 08601429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-12-03 [patent_title] => 'Method for connecting flip chip components' [patent_app_type] => utility [patent_app_number] => 13/007586 [patent_app_country] => US [patent_app_date] => 2011-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 7148 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13007586 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/007586
Method for connecting flip chip components Jan 13, 2011 Issued
Array ( [id] => 9555848 [patent_doc_number] => 08762920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Interconnection system and method' [patent_app_type] => utility [patent_app_number] => 12/960566 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 9923 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12960566 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/960566
Interconnection system and method Dec 5, 2010 Issued
Array ( [id] => 10577502 [patent_doc_number] => 09300157 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Context aware battery charging' [patent_app_type] => utility [patent_app_number] => 13/989502 [patent_app_country] => US [patent_app_date] => 2010-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5293 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13989502 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/989502
Context aware battery charging Nov 24, 2010 Issued
Array ( [id] => 6004186 [patent_doc_number] => 20110057333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-10 [patent_title] => 'METHOD FOR THE REAL-TIME MONITORING OF INTEGRATED CIRCUIT MANUFACTURE THROUGH LOCALIZED MONITORING STRUCTURES IN OPC MODEL SPACE' [patent_app_type] => utility [patent_app_number] => 12/946766 [patent_app_country] => US [patent_app_date] => 2010-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7068 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20110057333.pdf [firstpage_image] =>[orig_patent_app_number] => 12946766 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/946766
Method for the real-time monitoring of integrated circuit manufacture through localized monitoring structures in OPC model space Nov 14, 2010 Issued
Array ( [id] => 5991021 [patent_doc_number] => 20110099526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'Pattern Selection for Full-Chip Source and Mask Optimization' [patent_app_type] => utility [patent_app_number] => 12/914946 [patent_app_country] => US [patent_app_date] => 2010-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9372 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20110099526.pdf [firstpage_image] =>[orig_patent_app_number] => 12914946 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/914946
Pattern selection for full-chip source and mask optimization Oct 27, 2010 Issued
Array ( [id] => 9500240 [patent_doc_number] => 08739082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-27 [patent_title] => 'Method of pattern selection for source and mask optimization' [patent_app_type] => utility [patent_app_number] => 13/505286 [patent_app_country] => US [patent_app_date] => 2010-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13258 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13505286 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/505286
Method of pattern selection for source and mask optimization Oct 25, 2010 Issued
Array ( [id] => 8162793 [patent_doc_number] => 20120102448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-26 [patent_title] => 'Systems, Methods, and Programs for Leakage Power and Timing Optimization in Integrated Circuit Designs' [patent_app_type] => utility [patent_app_number] => 12/911156 [patent_app_country] => US [patent_app_date] => 2010-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11971 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20120102448.pdf [firstpage_image] =>[orig_patent_app_number] => 12911156 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/911156
Systems, methods, and programs for leakage power and timing optimization in integrated circuit designs Oct 24, 2010 Issued
Array ( [id] => 6057682 [patent_doc_number] => 20110113398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'Method and System for Providing Secondary Power Pins in Integrated Circuit Design' [patent_app_type] => utility [patent_app_number] => 12/910336 [patent_app_country] => US [patent_app_date] => 2010-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4681 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113398.pdf [firstpage_image] =>[orig_patent_app_number] => 12910336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/910336
Providing secondary power pins in integrated circuit design Oct 21, 2010 Issued
Array ( [id] => 10056798 [patent_doc_number] => 09096140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-04 [patent_title] => 'Management of the recharging of a set of batteries' [patent_app_type] => utility [patent_app_number] => 13/504375 [patent_app_country] => US [patent_app_date] => 2010-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3203 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13504375 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/504375
Management of the recharging of a set of batteries Oct 19, 2010 Issued
Array ( [id] => 8143755 [patent_doc_number] => 20120096424 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'Interconnect and Transistor Reliability Analysis for Deep Sub-Micron Designs' [patent_app_type] => utility [patent_app_number] => 12/907316 [patent_app_country] => US [patent_app_date] => 2010-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7558 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096424.pdf [firstpage_image] =>[orig_patent_app_number] => 12907316 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/907316
Interconnect and transistor reliability analysis for deep sub-micron designs Oct 18, 2010 Issued
Array ( [id] => 8414789 [patent_doc_number] => 20120242289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'METHOD FOR PRECISE POWER PREDICTION FOR BATTERY PACKS' [patent_app_type] => utility [patent_app_number] => 13/499145 [patent_app_country] => US [patent_app_date] => 2010-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5490 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13499145 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/499145
Method for precise power prediction for battery packs Oct 7, 2010 Issued
Array ( [id] => 8667689 [patent_doc_number] => 08381162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Method of adapting a layout of a standard cell of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/923726 [patent_app_country] => US [patent_app_date] => 2010-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5115 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12923726 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923726
Method of adapting a layout of a standard cell of an integrated circuit Oct 4, 2010 Issued
Array ( [id] => 9012611 [patent_doc_number] => 08527932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Method of optimizing automotive electrical wiring' [patent_app_type] => utility [patent_app_number] => 12/897116 [patent_app_country] => US [patent_app_date] => 2010-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4517 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12897116 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/897116
Method of optimizing automotive electrical wiring Oct 3, 2010 Issued
Array ( [id] => 6364780 [patent_doc_number] => 20100333058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES' [patent_app_type] => utility [patent_app_number] => 12/875517 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3811 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0333/20100333058.pdf [firstpage_image] =>[orig_patent_app_number] => 12875517 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875517
METHOD FOR INCREASING THE MANUFACTURING YIELD OF PROGRAMMABLE LOGIC DEVICES Sep 2, 2010 Abandoned
Array ( [id] => 9348272 [patent_doc_number] => 08667435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-04 [patent_title] => 'Function symmetry-based optimization for physical synthesis of programmable integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/874993 [patent_app_country] => US [patent_app_date] => 2010-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7969 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12874993 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/874993
Function symmetry-based optimization for physical synthesis of programmable integrated circuits Sep 1, 2010 Issued
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