Search

Lars A. Olson

Examiner (ID: 5853, Phone: (571)272-6685 , Office: P/3617 )

Most Active Art Unit
3617
Art Unit(s)
3617, 3615
Total Applications
3322
Issued Applications
2755
Pending Applications
170
Abandoned Applications
427

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5960947 [patent_doc_number] => 20110185334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'ZONE-BASED LEAKAGE POWER OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/695556 [patent_app_country] => US [patent_app_date] => 2010-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6155 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185334.pdf [firstpage_image] =>[orig_patent_app_number] => 12695556 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/695556
Zone-based leakage power optimization Jan 27, 2010 Issued
Array ( [id] => 6498741 [patent_doc_number] => 20100201344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'Method of Measuring Setup Time with Consideration of Characteristic of Absorbing Clock Skew in a Pulse-Based Flip-Flop' [patent_app_type] => utility [patent_app_number] => 12/693146 [patent_app_country] => US [patent_app_date] => 2010-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6074 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0201/20100201344.pdf [firstpage_image] =>[orig_patent_app_number] => 12693146 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/693146
Method of measuring setup time with consideration of characteristic of absorbing clock skew in a pulse-based flip-flop Jan 24, 2010 Issued
Array ( [id] => 6445974 [patent_doc_number] => 20100189003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'TEST APPARATUS AND CIRCUIT APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/687086 [patent_app_country] => US [patent_app_date] => 2010-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5988 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0189/20100189003.pdf [firstpage_image] =>[orig_patent_app_number] => 12687086 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/687086
Test apparatus and circuit apparatus Jan 12, 2010 Issued
Array ( [id] => 7682404 [patent_doc_number] => 20100242007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'CELL-LIBRARY-FOR-STATISTICAL-TIMING-ANALYSIS CREATING APPARATUS AND STATISTICAL-TIMING ANALYZING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/685066 [patent_app_country] => US [patent_app_date] => 2010-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10596 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20100242007.pdf [firstpage_image] =>[orig_patent_app_number] => 12685066 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/685066
Cell-library-for-statistical-timing-analysis creating apparatus and statistical-timing analyzing apparatus Jan 10, 2010 Issued
Array ( [id] => 6647874 [patent_doc_number] => 20100175037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'METHOD, APPARATUS, AND PROGRAM FOR CORRECTING HOLD ERROR' [patent_app_type] => utility [patent_app_number] => 12/652196 [patent_app_country] => US [patent_app_date] => 2010-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6797 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20100175037.pdf [firstpage_image] =>[orig_patent_app_number] => 12652196 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/652196
METHOD, APPARATUS, AND PROGRAM FOR CORRECTING HOLD ERROR Jan 4, 2010 Abandoned
Array ( [id] => 8985285 [patent_doc_number] => 08516415 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-08-20 [patent_title] => 'Method and system for the condensed macro library creation' [patent_app_type] => utility [patent_app_number] => 12/650923 [patent_app_country] => US [patent_app_date] => 2009-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 2 [patent_no_of_words] => 3371 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12650923 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650923
Method and system for the condensed macro library creation Dec 30, 2009 Issued
Array ( [id] => 8461008 [patent_doc_number] => 08296694 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-10-23 [patent_title] => 'System and method for automated synthesis of circuit wrappers' [patent_app_type] => utility [patent_app_number] => 12/649816 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7561 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12649816 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649816
System and method for automated synthesis of circuit wrappers Dec 29, 2009 Issued
Array ( [id] => 8401538 [patent_doc_number] => 08271933 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-09-18 [patent_title] => 'Pin unspecific device planning for printed circuit board layout' [patent_app_type] => utility [patent_app_number] => 12/650346 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 9191 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12650346 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650346
Pin unspecific device planning for printed circuit board layout Dec 29, 2009 Issued
Array ( [id] => 8728488 [patent_doc_number] => 08407630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-26 [patent_title] => 'Modeling and cross correlation of design predicted criticalities for optimization of semiconductor manufacturing' [patent_app_type] => utility [patent_app_number] => 12/644478 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6667 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12644478 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/644478
Modeling and cross correlation of design predicted criticalities for optimization of semiconductor manufacturing Dec 21, 2009 Issued
Array ( [id] => 8678835 [patent_doc_number] => 08386972 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-26 [patent_title] => 'Method and apparatus for managing the configuration and functionality of a semiconductor design' [patent_app_type] => utility [patent_app_number] => 12/639911 [patent_app_country] => US [patent_app_date] => 2009-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 12072 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12639911 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/639911
Method and apparatus for managing the configuration and functionality of a semiconductor design Dec 15, 2009 Issued
Array ( [id] => 8403565 [patent_doc_number] => 20120235627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'BALANCING ELECTRICAL VOLTAGES OF GROUPS OF ELECTRICAL ACCUMULATOR UNITS' [patent_app_type] => utility [patent_app_number] => 13/509149 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4169 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13509149 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/509149
BALANCING ELECTRICAL VOLTAGES OF GROUPS OF ELECTRICAL ACCUMULATOR UNITS Nov 18, 2009 Abandoned
Array ( [id] => 6338589 [patent_doc_number] => 20100199238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'Systematic Method for Variable Layout Shrink' [patent_app_type] => utility [patent_app_number] => 12/617046 [patent_app_country] => US [patent_app_date] => 2009-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2990 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0199/20100199238.pdf [firstpage_image] =>[orig_patent_app_number] => 12617046 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/617046
Systematic method for variable layout shrink Nov 11, 2009 Issued
Array ( [id] => 5948834 [patent_doc_number] => 20110107146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-05 [patent_title] => 'Trace Reconstruction for Silicon Validation of Asynchronous Systems-on-Chip' [patent_app_type] => utility [patent_app_number] => 12/611156 [patent_app_country] => US [patent_app_date] => 2009-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20110107146.pdf [firstpage_image] =>[orig_patent_app_number] => 12611156 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/611156
Trace reconstruction for silicon validation of asynchronous systems-on-chip Nov 2, 2009 Issued
Array ( [id] => 9999124 [patent_doc_number] => 09043741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-26 [patent_title] => 'Legalizing a portion of a circuit layout' [patent_app_type] => utility [patent_app_number] => 12/609996 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5106 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12609996 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/609996
Legalizing a portion of a circuit layout Oct 29, 2009 Issued
Array ( [id] => 6032155 [patent_doc_number] => 20110055785 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'METHOD AND APPARATUS FOR PERFORMING REDUNDANT VIA INSERTION DURING CIRCUIT DESIGN' [patent_app_type] => utility [patent_app_number] => 12/608446 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11886 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055785.pdf [firstpage_image] =>[orig_patent_app_number] => 12608446 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/608446
Method and apparatus for performing redundant via insertion during circuit design Oct 28, 2009 Issued
Array ( [id] => 6344041 [patent_doc_number] => 20100085077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'FPGA WITH HYBRID INTERCONNECT' [patent_app_type] => utility [patent_app_number] => 12/608371 [patent_app_country] => US [patent_app_date] => 2009-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4091 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085077.pdf [firstpage_image] =>[orig_patent_app_number] => 12608371 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/608371
FPGA with hybrid interconnect Oct 28, 2009 Issued
Array ( [id] => 8343235 [patent_doc_number] => 08245175 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Routing variants in electronic design automation' [patent_app_type] => utility [patent_app_number] => 12/605046 [patent_app_country] => US [patent_app_date] => 2009-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6738 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12605046 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/605046
Routing variants in electronic design automation Oct 22, 2009 Issued
Array ( [id] => 9593020 [patent_doc_number] => 08782586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning' [patent_app_type] => utility [patent_app_number] => 12/582366 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 40 [patent_no_of_words] => 8121 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12582366 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582366
Method, system, and program product for routing an integrated circuit to be manufactured by doubled patterning Oct 19, 2009 Issued
Array ( [id] => 8120427 [patent_doc_number] => 08161436 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-17 [patent_title] => 'Method and system for transforming fork-join blocks in a hardware description language (HDL) specification' [patent_app_type] => utility [patent_app_number] => 12/582596 [patent_app_country] => US [patent_app_date] => 2009-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5032 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161436.pdf [firstpage_image] =>[orig_patent_app_number] => 12582596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/582596
Method and system for transforming fork-join blocks in a hardware description language (HDL) specification Oct 19, 2009 Issued
Array ( [id] => 7680895 [patent_doc_number] => 20100023913 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'METHOD FOR IC WIRING YIELD OPTIMIZATION, INCLUDING WIRE WIDENING DURING AND AFTER ROUTING' [patent_app_type] => utility [patent_app_number] => 12/572297 [patent_app_country] => US [patent_app_date] => 2009-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4349 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023913.pdf [firstpage_image] =>[orig_patent_app_number] => 12572297 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/572297
Method for IC wiring yield optimization, including wire widening during and after routing Oct 1, 2009 Issued
Menu