Search

Lars A. Olson

Examiner (ID: 5853, Phone: (571)272-6685 , Office: P/3617 )

Most Active Art Unit
3617
Art Unit(s)
3617, 3615
Total Applications
3322
Issued Applications
2755
Pending Applications
170
Abandoned Applications
427

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8319822 [patent_doc_number] => 08234617 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Method and system for re-using digital assertions in a mixed signal design' [patent_app_type] => utility [patent_app_number] => 12/571726 [patent_app_country] => US [patent_app_date] => 2009-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9380 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12571726 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/571726
Method and system for re-using digital assertions in a mixed signal design Sep 30, 2009 Issued
Array ( [id] => 6433670 [patent_doc_number] => 20100168895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'MASK VERIFICATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER READABLE MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/561626 [patent_app_country] => US [patent_app_date] => 2009-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4228 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20100168895.pdf [firstpage_image] =>[orig_patent_app_number] => 12561626 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/561626
MASK VERIFICATION METHOD, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND COMPUTER READABLE MEDIUM Sep 16, 2009 Abandoned
Array ( [id] => 8183368 [patent_doc_number] => 08181149 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-15 [patent_title] => 'Interface for managing multiple implementations of a functional block of a circuit design' [patent_app_type] => utility [patent_app_number] => 12/553726 [patent_app_country] => US [patent_app_date] => 2009-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4139 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/181/08181149.pdf [firstpage_image] =>[orig_patent_app_number] => 12553726 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/553726
Interface for managing multiple implementations of a functional block of a circuit design Sep 2, 2009 Issued
Array ( [id] => 5399912 [patent_doc_number] => 20090319975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'Method and system for the modular design and layout of integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/583706 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7013 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0319/20090319975.pdf [firstpage_image] =>[orig_patent_app_number] => 12583706 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583706
Method and system for the modular design and layout of integrated circuits Aug 24, 2009 Issued
Array ( [id] => 8297462 [patent_doc_number] => 08225264 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Method and system for the modular design and layout of integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/583545 [patent_app_country] => US [patent_app_date] => 2009-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 7021 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12583545 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583545
Method and system for the modular design and layout of integrated circuits Aug 20, 2009 Issued
Array ( [id] => 5395102 [patent_doc_number] => 20090315165 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'Method and system for the modular design and layout of integrated circuits' [patent_app_type] => utility [patent_app_number] => 12/583552 [patent_app_country] => US [patent_app_date] => 2009-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7013 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20090315165.pdf [firstpage_image] =>[orig_patent_app_number] => 12583552 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583552
Method and system for the modular design and layout of integrated circuits Aug 20, 2009 Issued
Array ( [id] => 5370082 [patent_doc_number] => 20090307641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS' [patent_app_type] => utility [patent_app_number] => 12/542625 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13251 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307641.pdf [firstpage_image] =>[orig_patent_app_number] => 12542625 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/542625
Fast evaluation of average critical area for IC layouts Aug 16, 2009 Issued
Array ( [id] => 5370085 [patent_doc_number] => 20090307644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'FAST EVALUATION OF AVERAGE CRITICAL AREA FOR IC LAYOUTS' [patent_app_type] => utility [patent_app_number] => 12/542621 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13235 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307644.pdf [firstpage_image] =>[orig_patent_app_number] => 12542621 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/542621
Fast evaluation of average critical area for IC layouts Aug 16, 2009 Issued
Array ( [id] => 5370081 [patent_doc_number] => 20090307640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'Methods and Devices for Independent Evaluation of Cell Integrity, Changes and Origin in Chip Design for Production Workflow' [patent_app_type] => utility [patent_app_number] => 12/536413 [patent_app_country] => US [patent_app_date] => 2009-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 41641 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0307/20090307640.pdf [firstpage_image] =>[orig_patent_app_number] => 12536413 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/536413
Methods and devices for independent evaluation of cell integrity, changes and origin in chip design for production workflow Aug 4, 2009 Issued
Array ( [id] => 8158507 [patent_doc_number] => 08171446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'Method for designing a semiconductor device by computing a number of vias, program therefor, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/511416 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9485 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/171/08171446.pdf [firstpage_image] =>[orig_patent_app_number] => 12511416 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/511416
Method for designing a semiconductor device by computing a number of vias, program therefor, and semiconductor device Jul 28, 2009 Issued
Array ( [id] => 8805045 [patent_doc_number] => 08443330 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Methods and systems for measuring and reducing clock skew using a clock distribution network' [patent_app_type] => utility [patent_app_number] => 12/511607 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4640 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12511607 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/511607
Methods and systems for measuring and reducing clock skew using a clock distribution network Jul 28, 2009 Issued
Array ( [id] => 7680909 [patent_doc_number] => 20100023899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE' [patent_app_type] => utility [patent_app_number] => 12/510182 [patent_app_country] => US [patent_app_date] => 2009-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023899.pdf [firstpage_image] =>[orig_patent_app_number] => 12510182 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/510182
Analysis of stress impact on transistor performance Jul 26, 2009 Issued
Array ( [id] => 6154296 [patent_doc_number] => 20110022997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'METHOD FOR CONJECTURING EFFECTIVE WIDTH AND EFFECTIVE LENGTH OF GATE' [patent_app_type] => utility [patent_app_number] => 12/509496 [patent_app_country] => US [patent_app_date] => 2009-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022997.pdf [firstpage_image] =>[orig_patent_app_number] => 12509496 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/509496
Method for conjecturing effective width and effective length of gate Jul 26, 2009 Issued
Array ( [id] => 6154266 [patent_doc_number] => 20110022994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'Determining Source Patterns for Use in Photolithography' [patent_app_type] => utility [patent_app_number] => 12/507336 [patent_app_country] => US [patent_app_date] => 2009-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8425 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20110022994.pdf [firstpage_image] =>[orig_patent_app_number] => 12507336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/507336
Determining source patterns for use in photolithography Jul 21, 2009 Issued
Array ( [id] => 7680899 [patent_doc_number] => 20100023909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'VOLTAGE FLUCTUATION ESTIMATING METHOD AND APPARATUS, SEMICONDUCTOR DEVICE OPERATION VERIFICATION APPARATUS, SEMICONDUCTOR DEVICE DESIGNING METHOD, PRINTED CIRCUIT BOARD DESIGNING METHOD, AND PROGRAM' [patent_app_type] => utility [patent_app_number] => 12/505616 [patent_app_country] => US [patent_app_date] => 2009-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5447 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20100023909.pdf [firstpage_image] =>[orig_patent_app_number] => 12505616 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/505616
Voltage fluctuation estimating method and apparatus, semiconductor device operation verification apparatus, semiconductor device designing method, printed circuit board designing method, and program Jul 19, 2009 Issued
Array ( [id] => 8208352 [patent_doc_number] => 08191019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Non-predicated to predicated conversion of asynchronous representations' [patent_app_type] => utility [patent_app_number] => 12/505296 [patent_app_country] => US [patent_app_date] => 2009-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6736 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/191/08191019.pdf [firstpage_image] =>[orig_patent_app_number] => 12505296 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/505296
Non-predicated to predicated conversion of asynchronous representations Jul 16, 2009 Issued
Array ( [id] => 8208358 [patent_doc_number] => 08191022 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-29 [patent_title] => 'Stochastic steady state circuit analyses' [patent_app_type] => utility [patent_app_number] => 12/503006 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 6487 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/191/08191022.pdf [firstpage_image] =>[orig_patent_app_number] => 12503006 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/503006
Stochastic steady state circuit analyses Jul 13, 2009 Issued
Array ( [id] => 8810440 [patent_doc_number] => 08448107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Method for piecewise hierarchical sequential verification' [patent_app_type] => utility [patent_app_number] => 13/127936 [patent_app_country] => US [patent_app_date] => 2009-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 7627 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13127936 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/127936
Method for piecewise hierarchical sequential verification Jul 7, 2009 Issued
Array ( [id] => 5550252 [patent_doc_number] => 20090284238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-19 [patent_title] => 'Re-programmable modular power management circuit' [patent_app_type] => utility [patent_app_number] => 12/459515 [patent_app_country] => US [patent_app_date] => 2009-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5438 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0284/20090284238.pdf [firstpage_image] =>[orig_patent_app_number] => 12459515 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/459515
Re-programmable modular power management circuit Jul 1, 2009 Issued
Array ( [id] => 5493854 [patent_doc_number] => 20090261882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-22 [patent_title] => 'Skewed Double Differential Pair Circuit for Offset Cancelllation' [patent_app_type] => utility [patent_app_number] => 12/494642 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5134 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20090261882.pdf [firstpage_image] =>[orig_patent_app_number] => 12494642 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494642
Skewed double differential pair circuit for offset cancellation Jun 29, 2009 Issued
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