
Lars A. Olson
Examiner (ID: 5853, Phone: (571)272-6685 , Office: P/3617 )
| Most Active Art Unit | 3617 |
| Art Unit(s) | 3617, 3615 |
| Total Applications | 3322 |
| Issued Applications | 2755 |
| Pending Applications | 170 |
| Abandoned Applications | 427 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 16788291
[patent_doc_number] => 10990725
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-27
[patent_title] => Clock-gating phase algebra for clock analysis
[patent_app_type] => utility
[patent_app_number] => 16/412186
[patent_app_country] => US
[patent_app_date] => 2019-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 18
[patent_no_of_words] => 16367
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412186
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/412186 | Clock-gating phase algebra for clock analysis | May 13, 2019 | Issued |
Array
(
[id] => 14782823
[patent_doc_number] => 20190266309
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => METHOD OF DESIGNING SEMICONDUCTOR DEVICE AND SYSTEM FOR IMPLEMENTING THE METHOD
[patent_app_type] => utility
[patent_app_number] => 16/410761
[patent_app_country] => US
[patent_app_date] => 2019-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5793
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16410761
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/410761 | Method of designing semiconductor device and system for implementing the method | May 12, 2019 | Issued |
Array
(
[id] => 14785853
[patent_doc_number] => 20190267824
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-29
[patent_title] => DECORATIVE AND WEARABLE POWER CHARGER WITH FLASHLIGHT FEATURE AND WIRELESS CHARGING CAPABILITIES
[patent_app_type] => utility
[patent_app_number] => 16/408677
[patent_app_country] => US
[patent_app_date] => 2019-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10283
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16408677
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/408677 | DECORATIVE AND WEARABLE POWER CHARGER WITH FLASHLIGHT FEATURE AND WIRELESS CHARGING CAPABILITIES | May 9, 2019 | Abandoned |
Array
(
[id] => 16699164
[patent_doc_number] => 10949768
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-03-16
[patent_title] => Constructing quantum processes for quantum processors
[patent_app_type] => utility
[patent_app_number] => 16/401848
[patent_app_country] => US
[patent_app_date] => 2019-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7874
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 39
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16401848
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/401848 | Constructing quantum processes for quantum processors | May 1, 2019 | Issued |
Array
(
[id] => 16292489
[patent_doc_number] => 10769341
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-09-08
[patent_title] => Method of placing macro cells and a simulated-evolution-based macro refinement method
[patent_app_type] => utility
[patent_app_number] => 16/390840
[patent_app_country] => US
[patent_app_date] => 2019-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 1360
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16390840
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/390840 | Method of placing macro cells and a simulated-evolution-based macro refinement method | Apr 21, 2019 | Issued |
Array
(
[id] => 16355530
[patent_doc_number] => 10796042
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-10-06
[patent_title] => Partial selection-based model extraction from circuit design layout
[patent_app_type] => utility
[patent_app_number] => 16/391122
[patent_app_country] => US
[patent_app_date] => 2019-04-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 17262
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16391122
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/391122 | Partial selection-based model extraction from circuit design layout | Apr 21, 2019 | Issued |
Array
(
[id] => 16355529
[patent_doc_number] => 10796041
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2020-10-06
[patent_title] => Compacting test patterns for IJTAG test
[patent_app_type] => utility
[patent_app_number] => 16/389733
[patent_app_country] => US
[patent_app_date] => 2019-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9621
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16389733
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/389733 | Compacting test patterns for IJTAG test | Apr 18, 2019 | Issued |
Array
(
[id] => 14689643
[patent_doc_number] => 20190243937
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-08
[patent_title] => METHOD OF PARAMETER CREATION
[patent_app_type] => utility
[patent_app_number] => 16/385420
[patent_app_country] => US
[patent_app_date] => 2019-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6973
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 407
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16385420
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/385420 | METHOD OF PARAMETER CREATION | Apr 15, 2019 | Abandoned |
Array
(
[id] => 16864635
[patent_doc_number] => 11023377
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA)
[patent_app_type] => utility
[patent_app_number] => 16/258366
[patent_app_country] => US
[patent_app_date] => 2019-01-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 11538
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16258366
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/258366 | Application mapping on hardened network-on-chip (NoC) of field-programmable gate array (FPGA) | Jan 24, 2019 | Issued |
Array
(
[id] => 16455485
[patent_doc_number] => 20200364911
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-19
[patent_title] => DEVICE AND METHOD FOR COMPARING GEOMETRIC FILES
[patent_app_type] => utility
[patent_app_number] => 16/961375
[patent_app_country] => US
[patent_app_date] => 2019-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4690
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 40
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16961375
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/961375 | Device and method for comparing geometric files | Jan 15, 2019 | Issued |
Array
(
[id] => 15185917
[patent_doc_number] => 20190363550
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-28
[patent_title] => BATTERY PACK SYSTEM, CONTROL METHOD THEREOF AND MANAGEMENT DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/243373
[patent_app_country] => US
[patent_app_date] => 2019-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9577
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 288
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243373
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/243373 | Battery pack system, control method thereof and management device | Jan 8, 2019 | Issued |
Array
(
[id] => 16706709
[patent_doc_number] => 10956644
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-23
[patent_title] => Integrated circuit design changes using through-silicon vias
[patent_app_type] => utility
[patent_app_number] => 16/243565
[patent_app_country] => US
[patent_app_date] => 2019-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10971
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 256
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243565
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/243565 | Integrated circuit design changes using through-silicon vias | Jan 8, 2019 | Issued |
Array
(
[id] => 16817976
[patent_doc_number] => 11002795
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-11
[patent_title] => Charger with battery diagnosis function and control method thereof
[patent_app_type] => utility
[patent_app_number] => 16/243511
[patent_app_country] => US
[patent_app_date] => 2019-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 6410
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16243511
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/243511 | Charger with battery diagnosis function and control method thereof | Jan 8, 2019 | Issued |
Array
(
[id] => 14539045
[patent_doc_number] => 20190205144
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-04
[patent_title] => FAST BOOT SYSTEMS AND METHODS FOR PROGRAMMABLE LOGIC DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/228647
[patent_app_country] => US
[patent_app_date] => 2018-12-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10954
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16228647
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/228647 | Fast boot systems and methods for programmable logic devices | Dec 19, 2018 | Issued |
Array
(
[id] => 14477275
[patent_doc_number] => 20190190287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-06-20
[patent_title] => APPARATUS AND METHOD FOR A PORTABLE-ELECTRONIC-DEVICE ADAPTER
[patent_app_type] => utility
[patent_app_number] => 16/221087
[patent_app_country] => US
[patent_app_date] => 2018-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6308
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221087
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/221087 | Apparatus and method for a portable-electronic-device adapter | Dec 13, 2018 | Issued |
Array
(
[id] => 16537089
[patent_doc_number] => 10879709
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-12-29
[patent_title] => Power management system and operating method thereof
[patent_app_type] => utility
[patent_app_number] => 16/220180
[patent_app_country] => US
[patent_app_date] => 2018-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 7859
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 480
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220180
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/220180 | Power management system and operating method thereof | Dec 13, 2018 | Issued |
Array
(
[id] => 16741840
[patent_doc_number] => 10966805
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-06
[patent_title] => Apparatus and methods for supporting and charging a dental device
[patent_app_type] => utility
[patent_app_number] => 16/220991
[patent_app_country] => US
[patent_app_date] => 2018-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4357
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16220991
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/220991 | Apparatus and methods for supporting and charging a dental device | Dec 13, 2018 | Issued |
Array
(
[id] => 16605425
[patent_doc_number] => 10906414
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-02-02
[patent_title] => Systems and methods for restarting electrified vehicle charging without unplugging
[patent_app_type] => utility
[patent_app_number] => 16/218635
[patent_app_country] => US
[patent_app_date] => 2018-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4853
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218635
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/218635 | Systems and methods for restarting electrified vehicle charging without unplugging | Dec 12, 2018 | Issued |
Array
(
[id] => 16322395
[patent_doc_number] => 10782354
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-09-22
[patent_title] => Low voltage threshold adjusting method
[patent_app_type] => utility
[patent_app_number] => 16/219910
[patent_app_country] => US
[patent_app_date] => 2018-12-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2387
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219910
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/219910 | Low voltage threshold adjusting method | Dec 12, 2018 | Issued |
Array
(
[id] => 16801781
[patent_doc_number] => 10996723
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-05-04
[patent_title] => Synchronized reset for a circuit emulator
[patent_app_type] => utility
[patent_app_number] => 16/218079
[patent_app_country] => US
[patent_app_date] => 2018-12-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5897
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218079
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/218079 | Synchronized reset for a circuit emulator | Dec 11, 2018 | Issued |