Search

Laura C. Powers

Examiner (ID: 3821)

Most Active Art Unit
1785
Art Unit(s)
1785
Total Applications
657
Issued Applications
313
Pending Applications
74
Abandoned Applications
282

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11013232 [patent_doc_number] => 20160210185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'METHOD AND APPARATUS FOR WIRELESS COMMUNICATION' [patent_app_type] => utility [patent_app_number] => 14/601756 [patent_app_country] => US [patent_app_date] => 2015-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3231 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14601756 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/601756
METHOD AND APPARATUS FOR WIRELESS COMMUNICATION Jan 20, 2015
Array ( [id] => 11014082 [patent_doc_number] => 20160211035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-21 [patent_title] => 'Selective Online Burn-In with Adaptive and Delayed Verification Methods for Memory' [patent_app_type] => utility [patent_app_number] => 14/600342 [patent_app_country] => US [patent_app_date] => 2015-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 17302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14600342 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/600342
Selective online burn-in with adaptive and delayed verification methods for memory Jan 19, 2015 Issued
Array ( [id] => 12431706 [patent_doc_number] => 09977080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-22 [patent_title] => Generating test sets for diagnosing scan chain failures [patent_app_type] => utility [patent_app_number] => 14/595021 [patent_app_country] => US [patent_app_date] => 2015-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 16191 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595021 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/595021
Generating test sets for diagnosing scan chain failures Jan 11, 2015 Issued
Array ( [id] => 11308264 [patent_doc_number] => 09515675 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => 'Interface circuit operating to recover error of transmitted data' [patent_app_type] => utility [patent_app_number] => 14/593585 [patent_app_country] => US [patent_app_date] => 2015-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12044 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14593585 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/593585
Interface circuit operating to recover error of transmitted data Jan 8, 2015 Issued
Array ( [id] => 11278169 [patent_doc_number] => 09494647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-15 [patent_title] => 'Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects' [patent_app_type] => utility [patent_app_number] => 14/588368 [patent_app_country] => US [patent_app_date] => 2014-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 8941 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14588368 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/588368
Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects Dec 30, 2014 Issued
Array ( [id] => 10816219 [patent_doc_number] => 20160162380 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'IMPLEMENTING PROCESSOR FUNCTIONAL VERIFICATION BY GENERATING AND RUNNING CONSTRAINED RANDOM IRRITATOR TESTS FOR MULTIPLE PROCESSOR SYSTEM AND PROCESSOR CORE WITH MULTIPLE THREADS' [patent_app_type] => utility [patent_app_number] => 14/562908 [patent_app_country] => US [patent_app_date] => 2014-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5457 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14562908 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/562908
Implementing processor functional verification by generating and running constrained random irritator tests for multiple processor system and processor core with multiple threads Dec 7, 2014 Issued
Array ( [id] => 11278166 [patent_doc_number] => 09494644 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-15 [patent_title] => 'Semiconductor device including memory circuit and logic array' [patent_app_type] => utility [patent_app_number] => 14/542859 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 28 [patent_no_of_words] => 19992 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14542859 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/542859
Semiconductor device including memory circuit and logic array Nov 16, 2014 Issued
Array ( [id] => 12534288 [patent_doc_number] => 10008286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-26 [patent_title] => Self-testing data storage devices and methods [patent_app_type] => utility [patent_app_number] => 14/536472 [patent_app_country] => US [patent_app_date] => 2014-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8335 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14536472 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/536472
Self-testing data storage devices and methods Nov 6, 2014 Issued
Array ( [id] => 10157536 [patent_doc_number] => 09189315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-11-17 [patent_title] => 'Channel quality monitoring and method for qualifying a storage channel using an iterative decoder' [patent_app_type] => utility [patent_app_number] => 14/511695 [patent_app_country] => US [patent_app_date] => 2014-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 11055 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14511695 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/511695
Channel quality monitoring and method for qualifying a storage channel using an iterative decoder Oct 9, 2014 Issued
Array ( [id] => 11488544 [patent_doc_number] => 09594615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-14 [patent_title] => 'Estimating flash quality using selective error emphasis' [patent_app_type] => utility [patent_app_number] => 14/501081 [patent_app_country] => US [patent_app_date] => 2014-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6997 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14501081 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/501081
Estimating flash quality using selective error emphasis Sep 29, 2014 Issued
Array ( [id] => 11264957 [patent_doc_number] => 09489254 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-11-08 [patent_title] => 'Verification of erasure encoded fragments' [patent_app_type] => utility [patent_app_number] => 14/500576 [patent_app_country] => US [patent_app_date] => 2014-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14500576 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/500576
Verification of erasure encoded fragments Sep 28, 2014 Issued
Array ( [id] => 11933257 [patent_doc_number] => 09800266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-24 [patent_title] => 'Low density parity check encoder having length of 64800 and code rate of 4/15, and low density parity check encoding method using the same' [patent_app_type] => utility [patent_app_number] => 14/496654 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 7042 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 815 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14496654 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/496654
Low density parity check encoder having length of 64800 and code rate of 4/15, and low density parity check encoding method using the same Sep 24, 2014 Issued
Array ( [id] => 10631333 [patent_doc_number] => 09349488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-24 [patent_title] => 'Semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 14/495988 [patent_app_country] => US [patent_app_date] => 2014-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5279 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14495988 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/495988
Semiconductor memory apparatus Sep 24, 2014 Issued
Array ( [id] => 10448761 [patent_doc_number] => 20150333775 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-19 [patent_title] => 'Frozen-Bit Selection for a Polar Code Decoder' [patent_app_type] => utility [patent_app_number] => 14/482772 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14482772 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/482772
Frozen-Bit Selection for a Polar Code Decoder Sep 9, 2014 Abandoned
Array ( [id] => 11007849 [patent_doc_number] => 20160204801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-07-14 [patent_title] => 'DATA PROCESSING DEVICE AND DATA PROCESSING METHOD' [patent_app_type] => utility [patent_app_number] => 14/913901 [patent_app_country] => US [patent_app_date] => 2014-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 37570 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14913901 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/913901
DATA PROCESSING DEVICE AND DATA PROCESSING METHOD Sep 4, 2014 Abandoned
Array ( [id] => 10454168 [patent_doc_number] => 20150339183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'CONTROLLER, STORAGE DEVICE, AND CONTROL METHOD' [patent_app_type] => utility [patent_app_number] => 14/477432 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14477432 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/477432
CONTROLLER, STORAGE DEVICE, AND CONTROL METHOD Sep 3, 2014 Abandoned
Array ( [id] => 11803056 [patent_doc_number] => 09543983 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Decoding method, memory storage device and memory control circuit unit' [patent_app_type] => utility [patent_app_number] => 14/475585 [patent_app_country] => US [patent_app_date] => 2014-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 10506 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14475585 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/475585
Decoding method, memory storage device and memory control circuit unit Sep 2, 2014 Issued
Array ( [id] => 10717955 [patent_doc_number] => 20160064102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'FAST AUTO SHIFT OF FAILING MEMORY DIAGNOSTICS DATA USING PATTERN DETECTION' [patent_app_type] => utility [patent_app_number] => 14/468999 [patent_app_country] => US [patent_app_date] => 2014-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14468999 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/468999
Fast auto shift of failing memory diagnostics data using pattern detection Aug 25, 2014 Issued
Array ( [id] => 11702519 [patent_doc_number] => 09692456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-06-27 [patent_title] => 'Product coded modulation scheme based on E8 lattice and binary and nonbinary codes' [patent_app_type] => utility [patent_app_number] => 14/466372 [patent_app_country] => US [patent_app_date] => 2014-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14466372 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/466372
Product coded modulation scheme based on E8 lattice and binary and nonbinary codes Aug 21, 2014 Issued
Array ( [id] => 10221689 [patent_doc_number] => 20150106682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'CUMULATIVE ERROR DETECTION IN DATA TRANSMISSION' [patent_app_type] => utility [patent_app_number] => 14/462205 [patent_app_country] => US [patent_app_date] => 2014-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8084 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14462205 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/462205
Cumulative error detection in data transmission Aug 17, 2014 Issued
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