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Laura Mary Menz

Examiner (ID: 16260)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2273
Issued Applications
1951
Pending Applications
152
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18150100 [patent_doc_number] => 20230023957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-26 [patent_title] => Communication Between Stacked Die [patent_app_type] => utility [patent_app_number] => 17/936153 [patent_app_country] => US [patent_app_date] => 2022-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18626 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936153
Communication between stacked die Sep 27, 2022 Issued
Array ( [id] => 18141776 [patent_doc_number] => 20230015619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SURFACE FINISHES WITH LOW RBTV FOR FINE AND MIXED BUMP PITCH ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 17/952080 [patent_app_country] => US [patent_app_date] => 2022-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10663 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17952080 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/952080
Surface finishes with low RBTV for fine and mixed bump pitch architectures Sep 22, 2022 Issued
Array ( [id] => 19054781 [patent_doc_number] => 20240096750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SELF-ALIGNED BACKSIDE CONTACT MODULE FOR 3DIC APPLICATION [patent_app_type] => utility [patent_app_number] => 17/933187 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17933187 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/933187
SELF-ALIGNED BACKSIDE CONTACT MODULE FOR 3DIC APPLICATION Sep 18, 2022 Pending
Array ( [id] => 19054781 [patent_doc_number] => 20240096750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SELF-ALIGNED BACKSIDE CONTACT MODULE FOR 3DIC APPLICATION [patent_app_type] => utility [patent_app_number] => 17/933187 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17933187 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/933187
SELF-ALIGNED BACKSIDE CONTACT MODULE FOR 3DIC APPLICATION Sep 18, 2022 Pending
Array ( [id] => 19054781 [patent_doc_number] => 20240096750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => SELF-ALIGNED BACKSIDE CONTACT MODULE FOR 3DIC APPLICATION [patent_app_type] => utility [patent_app_number] => 17/933187 [patent_app_country] => US [patent_app_date] => 2022-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7375 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17933187 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/933187
SELF-ALIGNED BACKSIDE CONTACT MODULE FOR 3DIC APPLICATION Sep 18, 2022 Pending
Array ( [id] => 19054821 [patent_doc_number] => 20240096790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => PORT LANDING-FREE LOW-SKEW SIGNAL DISTRIBUTION WITH BACKSIDE METALLIZATION AND BURIED RAIL [patent_app_type] => utility [patent_app_number] => 17/932500 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932500 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932500
PORT LANDING-FREE LOW-SKEW SIGNAL DISTRIBUTION WITH BACKSIDE METALLIZATION AND BURIED RAIL Sep 14, 2022 Pending
Array ( [id] => 19054821 [patent_doc_number] => 20240096790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => PORT LANDING-FREE LOW-SKEW SIGNAL DISTRIBUTION WITH BACKSIDE METALLIZATION AND BURIED RAIL [patent_app_type] => utility [patent_app_number] => 17/932500 [patent_app_country] => US [patent_app_date] => 2022-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -28 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17932500 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/932500
PORT LANDING-FREE LOW-SKEW SIGNAL DISTRIBUTION WITH BACKSIDE METALLIZATION AND BURIED RAIL Sep 14, 2022 Pending
Array ( [id] => 18267725 [patent_doc_number] => 20230088967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => INTEGRATED CIRCUIT INCLUDING STANDARD CELLS AND AT LEAST ONE CAPACITIVE FILLING STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/944793 [patent_app_country] => US [patent_app_date] => 2022-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5611 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944793 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944793
Integrated circuit including standard cells and at least one capacitive filling structure Sep 13, 2022 Issued
Array ( [id] => 19038437 [patent_doc_number] => 20240088252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => GATE ALL AROUND TRANSISTORS WITH HETEROGENEOUS CHANNELS [patent_app_type] => utility [patent_app_number] => 17/930706 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17930706 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/930706
GATE ALL AROUND TRANSISTORS WITH HETEROGENEOUS CHANNELS Sep 7, 2022 Pending
Array ( [id] => 19023198 [patent_doc_number] => 20240079369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => CONNECTING SEMICONDUCTOR DIES THROUGH TRACES [patent_app_type] => utility [patent_app_number] => 17/938917 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17938917 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/938917
CONNECTING SEMICONDUCTOR DIES THROUGH TRACES Sep 5, 2022 Pending
Array ( [id] => 19023147 [patent_doc_number] => 20240079318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => NAND DIE WITH RDL FOR ALTERED BOND WIRE BANDWIDTH IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/903965 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7284 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17903965 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/903965
NAND DIE WITH RDL FOR ALTERED BOND WIRE BANDWIDTH IN MEMORY DEVICES Sep 5, 2022 Pending
Array ( [id] => 18281723 [patent_doc_number] => 20230097195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => METHOD FOR INSPECTING CHEMICAL SOLUTION, METHOD FOR PRODUCING CHEMICAL SOLUTION, METHOD FOR CONTROLLING CHEMICAL SOLUTION, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, METHOD FOR INSPECTING RESIST COMPOSITION, METHOD FOR PRODUCING RESIST COMPOSITION, METHOD FOR CONTROLLING RESIST COMPOSITION, AND METHOD FOR CHECKING CONTAMINATION STATUS OF SEMICONDUCTOR MANUFACTURING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/902899 [patent_app_country] => US [patent_app_date] => 2022-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25930 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902899
Method for inspecting chemical solution, method for producing chemical solution, method for controlling chemical solution, method for producing semiconductor device, method for inspecting resist composition, method for producing resist composition, method for controlling resist composition, and method for checking contamination status of semiconductor manufacturing apparatus Sep 4, 2022 Issued
Array ( [id] => 18281723 [patent_doc_number] => 20230097195 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => METHOD FOR INSPECTING CHEMICAL SOLUTION, METHOD FOR PRODUCING CHEMICAL SOLUTION, METHOD FOR CONTROLLING CHEMICAL SOLUTION, METHOD FOR PRODUCING SEMICONDUCTOR DEVICE, METHOD FOR INSPECTING RESIST COMPOSITION, METHOD FOR PRODUCING RESIST COMPOSITION, METHOD FOR CONTROLLING RESIST COMPOSITION, AND METHOD FOR CHECKING CONTAMINATION STATUS OF SEMICONDUCTOR MANUFACTURING APPARATUS [patent_app_type] => utility [patent_app_number] => 17/902899 [patent_app_country] => US [patent_app_date] => 2022-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25930 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17902899 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/902899
Method for inspecting chemical solution, method for producing chemical solution, method for controlling chemical solution, method for producing semiconductor device, method for inspecting resist composition, method for producing resist composition, method for controlling resist composition, and method for checking contamination status of semiconductor manufacturing apparatus Sep 4, 2022 Issued
Array ( [id] => 19494345 [patent_doc_number] => 12113069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Thermal extraction of single layer transfer integrated circuits [patent_app_type] => utility [patent_app_number] => 17/901189 [patent_app_country] => US [patent_app_date] => 2022-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 9798 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17901189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/901189
Thermal extraction of single layer transfer integrated circuits Aug 31, 2022 Issued
Array ( [id] => 19981856 [patent_doc_number] => 12349358 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Semiconductor device and semiconductor storage device [patent_app_type] => utility [patent_app_number] => 17/897065 [patent_app_country] => US [patent_app_date] => 2022-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 3255 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17897065 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/897065
Semiconductor device and semiconductor storage device Aug 25, 2022 Issued
Array ( [id] => 18488481 [patent_doc_number] => 20230215829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => SEMICONDUCTOR PACKAGE [patent_app_type] => utility [patent_app_number] => 17/895223 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13926 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895223 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895223
Semiconductor package Aug 24, 2022 Issued
Array ( [id] => 19007878 [patent_doc_number] => 20240071949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => TWO-PIECE TYPE STIFFENER STRUCTURE WITH BEVELED SURFACE FOR DELAMINATION REDUCTION AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/895306 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15443 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895306 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895306
TWO-PIECE TYPE STIFFENER STRUCTURE WITH BEVELED SURFACE FOR DELAMINATION REDUCTION AND METHODS FOR FORMING THE SAME Aug 24, 2022 Pending
Array ( [id] => 19007931 [patent_doc_number] => 20240072002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => SEMICONDUCTOR DEVICES, ASSEMBLIES, AND ASSOCIATED METHODS [patent_app_type] => utility [patent_app_number] => 17/893941 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893941
SEMICONDUCTOR DEVICES, ASSEMBLIES, AND ASSOCIATED METHODS Aug 22, 2022 Pending
Array ( [id] => 18661272 [patent_doc_number] => 20230307285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => ISOLATION STRUCTURES IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/821042 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821042 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/821042
Isolation structures in semiconductor devices Aug 18, 2022 Issued
Array ( [id] => 18661272 [patent_doc_number] => 20230307285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => ISOLATION STRUCTURES IN SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 17/821042 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10465 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17821042 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/821042
Isolation structures in semiconductor devices Aug 18, 2022 Issued
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