Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 876130 [patent_doc_number] => 07358159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Method for manufacturing ZnTe compound semiconductor single crystal ZnTe compound semiconductor single crystal, and semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/472446 [patent_app_country] => US [patent_app_date] => 2002-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11733 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/358/07358159.pdf [firstpage_image] =>[orig_patent_app_number] => 10472446 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/472446
Method for manufacturing ZnTe compound semiconductor single crystal ZnTe compound semiconductor single crystal, and semiconductor device Mar 19, 2002 Issued
Array ( [id] => 6538609 [patent_doc_number] => 20020137235 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-26 [patent_title] => 'Electronic devices comprising thin-film transistors, and their manufacture' [patent_app_type] => new [patent_app_number] => 10/099680 [patent_app_country] => US [patent_app_date] => 2002-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4408 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0137/20020137235.pdf [firstpage_image] =>[orig_patent_app_number] => 10099680 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/099680
Manufacture of electronic devices comprising thin-film transistors Mar 14, 2002 Issued
Array ( [id] => 6730325 [patent_doc_number] => 20030186515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-02 [patent_title] => 'Methods for simultaneously depositing layers over pluralities of discrete semiconductor substrate' [patent_app_type] => new [patent_app_number] => 10/099216 [patent_app_country] => US [patent_app_date] => 2002-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6395 [patent_no_of_claims] => 81 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20030186515.pdf [firstpage_image] =>[orig_patent_app_number] => 10099216 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/099216
Methods for treating semiconductor substrates Mar 12, 2002 Issued
Array ( [id] => 1014581 [patent_doc_number] => 06893923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Reduced mask count process for manufacture of mosgated device' [patent_app_type] => utility [patent_app_number] => 10/094835 [patent_app_country] => US [patent_app_date] => 2002-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1209 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/893/06893923.pdf [firstpage_image] =>[orig_patent_app_number] => 10094835 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/094835
Reduced mask count process for manufacture of mosgated device Mar 6, 2002 Issued
Array ( [id] => 6044365 [patent_doc_number] => 20020167060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-14 [patent_title] => 'Module and electronic device' [patent_app_type] => new [patent_app_number] => 10/085669 [patent_app_country] => US [patent_app_date] => 2002-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3110 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20020167060.pdf [firstpage_image] =>[orig_patent_app_number] => 10085669 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/085669
Module and electronic device Feb 26, 2002 Issued
Array ( [id] => 1165005 [patent_doc_number] => 06756242 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Method of modifying an integrated circuit' [patent_app_type] => B1 [patent_app_number] => 10/018867 [patent_app_country] => US [patent_app_date] => 2002-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 38 [patent_no_of_words] => 8325 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/756/06756242.pdf [firstpage_image] =>[orig_patent_app_number] => 10018867 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/018867
Method of modifying an integrated circuit Feb 26, 2002 Issued
Array ( [id] => 6158017 [patent_doc_number] => 20020146870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'POLYSILICON THIN FILM TRANSISTOR WITH A SELF-ALIGNED LDD STRUCTURE' [patent_app_type] => new [patent_app_number] => 10/084816 [patent_app_country] => US [patent_app_date] => 2002-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1733 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20020146870.pdf [firstpage_image] =>[orig_patent_app_number] => 10084816 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/084816
Polysilicon thin film transistor with a self-aligned LDD structure Feb 24, 2002 Issued
Array ( [id] => 1327296 [patent_doc_number] => 06599829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-29 [patent_title] => 'Method for photoresist strip, sidewall polymer removal and passivation for aluminum metallization' [patent_app_type] => B2 [patent_app_number] => 10/082759 [patent_app_country] => US [patent_app_date] => 2002-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 5472 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/599/06599829.pdf [firstpage_image] =>[orig_patent_app_number] => 10082759 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/082759
Method for photoresist strip, sidewall polymer removal and passivation for aluminum metallization Feb 24, 2002 Issued
09/890376 Method for fabricating thin film semiconductor devices Feb 20, 2002 Abandoned
Array ( [id] => 1591803 [patent_doc_number] => 06483368 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Addressable diode isolated thin film cell array' [patent_app_type] => B2 [patent_app_number] => 10/081559 [patent_app_country] => US [patent_app_date] => 2002-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3706 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483368.pdf [firstpage_image] =>[orig_patent_app_number] => 10081559 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/081559
Addressable diode isolated thin film cell array Feb 19, 2002 Issued
Array ( [id] => 712250 [patent_doc_number] => 07057257 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-06 [patent_title] => 'Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry' [patent_app_type] => utility [patent_app_number] => 10/071453 [patent_app_country] => US [patent_app_date] => 2002-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2612 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/057/07057257.pdf [firstpage_image] =>[orig_patent_app_number] => 10071453 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/071453
Semiconductor processing methods of forming transistors, semiconductor processing methods of forming dynamic random access memory circuitry, and related integrated circuitry Feb 7, 2002 Issued
Array ( [id] => 6843230 [patent_doc_number] => 20030148577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Controlled alignment of catalytically grown nanostructures in a large-scale synthesis process' [patent_app_type] => new [patent_app_number] => 10/068795 [patent_app_country] => US [patent_app_date] => 2002-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6435 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20030148577.pdf [firstpage_image] =>[orig_patent_app_number] => 10068795 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/068795
Controlled non-normal alignment of catalytically grown nanostructures in a large-scale synthesis process Feb 5, 2002 Issued
Array ( [id] => 588566 [patent_doc_number] => 07442968 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Chip on film (COF) package having test pad for testing electrical function of chip and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 10/061099 [patent_app_country] => US [patent_app_date] => 2002-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3325 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/442/07442968.pdf [firstpage_image] =>[orig_patent_app_number] => 10061099 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/061099
Chip on film (COF) package having test pad for testing electrical function of chip and method for manufacturing same Jan 31, 2002 Issued
Array ( [id] => 1340465 [patent_doc_number] => 06593616 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Buried bit line memory circuitry' [patent_app_type] => B2 [patent_app_number] => 10/060894 [patent_app_country] => US [patent_app_date] => 2002-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 3817 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593616.pdf [firstpage_image] =>[orig_patent_app_number] => 10060894 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/060894
Buried bit line memory circuitry Jan 28, 2002 Issued
Array ( [id] => 578810 [patent_doc_number] => 07459757 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-02 [patent_title] => 'Transistor structures' [patent_app_type] => utility [patent_app_number] => 10/050348 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2522 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/459/07459757.pdf [firstpage_image] =>[orig_patent_app_number] => 10050348 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050348
Transistor structures Jan 14, 2002 Issued
Array ( [id] => 602403 [patent_doc_number] => 07432166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Methods of forming a nitrogen enriched region' [patent_app_type] => utility [patent_app_number] => 10/050373 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2522 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/432/07432166.pdf [firstpage_image] =>[orig_patent_app_number] => 10050373 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050373
Methods of forming a nitrogen enriched region Jan 14, 2002 Issued
Array ( [id] => 5986522 [patent_doc_number] => 20020098710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Methods Of Forming Transistors' [patent_app_type] => new [patent_app_number] => 10/050347 [patent_app_country] => US [patent_app_date] => 2002-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2507 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20020098710.pdf [firstpage_image] =>[orig_patent_app_number] => 10050347 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050347
Methods of forming transistors Jan 14, 2002 Issued
Array ( [id] => 5828770 [patent_doc_number] => 20020068430 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Methods of forming void regions, dielectric regions and capacitor constructions' [patent_app_type] => new [patent_app_number] => 10/044206 [patent_app_country] => US [patent_app_date] => 2002-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4606 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 22 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20020068430.pdf [firstpage_image] =>[orig_patent_app_number] => 10044206 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/044206
Methods of forming void regions, dielectric regions and capacitor constructions Jan 10, 2002 Issued
Array ( [id] => 6359027 [patent_doc_number] => 20020058364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-16 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => new [patent_app_number] => 10/035205 [patent_app_country] => US [patent_app_date] => 2002-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20020058364.pdf [firstpage_image] =>[orig_patent_app_number] => 10035205 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035205
Semiconductor device and manufacturing method thereof Jan 3, 2002 Issued
Array ( [id] => 1588727 [patent_doc_number] => 06482685 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method for fabricating a low temperature polysilicon thin film transistor incorporating multi-layer channel passivation step' [patent_app_type] => B1 [patent_app_number] => 10/037014 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 13 [patent_no_of_words] => 4513 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482685.pdf [firstpage_image] =>[orig_patent_app_number] => 10037014 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/037014
Method for fabricating a low temperature polysilicon thin film transistor incorporating multi-layer channel passivation step Dec 30, 2001 Issued
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