Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1346669 [patent_doc_number] => 06583057 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-24 [patent_title] => 'Method of forming a semiconductor device having a layer deposited by varying flow of reactants' [patent_app_type] => B1 [patent_app_number] => 09/211165 [patent_app_country] => US [patent_app_date] => 1998-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3283 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/583/06583057.pdf [firstpage_image] =>[orig_patent_app_number] => 09211165 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/211165
Method of forming a semiconductor device having a layer deposited by varying flow of reactants Dec 13, 1998 Issued
Array ( [id] => 4420552 [patent_doc_number] => 06225210 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'High density capping layers with improved adhesion to copper interconnects' [patent_app_type] => 1 [patent_app_number] => 9/207675 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3899 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225210.pdf [firstpage_image] =>[orig_patent_app_number] => 207675 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/207675
High density capping layers with improved adhesion to copper interconnects Dec 8, 1998 Issued
Array ( [id] => 4306179 [patent_doc_number] => 06241907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method and system for providing a package for decapsulating a chip-scale package' [patent_app_type] => 1 [patent_app_number] => 9/208824 [patent_app_country] => US [patent_app_date] => 1998-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2833 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/241/06241907.pdf [firstpage_image] =>[orig_patent_app_number] => 208824 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/208824
Method and system for providing a package for decapsulating a chip-scale package Dec 8, 1998 Issued
Array ( [id] => 4287275 [patent_doc_number] => 06268291 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method for forming electromigration-resistant structures by doping' [patent_app_type] => 1 [patent_app_number] => 9/204185 [patent_app_country] => US [patent_app_date] => 1998-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 15 [patent_no_of_words] => 7337 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268291.pdf [firstpage_image] =>[orig_patent_app_number] => 204185 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204185
Method for forming electromigration-resistant structures by doping Dec 2, 1998 Issued
Array ( [id] => 4132127 [patent_doc_number] => 06121156 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Contact monitor, method of forming same and method of analyzing contact-, via-and/or trench-forming processes in an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/204215 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 8621 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121156.pdf [firstpage_image] =>[orig_patent_app_number] => 204215 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/204215
Contact monitor, method of forming same and method of analyzing contact-, via-and/or trench-forming processes in an integrated circuit Dec 1, 1998 Issued
Array ( [id] => 1485125 [patent_doc_number] => 06365438 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Process for manufacturing semiconductor package and circuit board assembly' [patent_app_type] => B1 [patent_app_number] => 09/194735 [patent_app_country] => US [patent_app_date] => 1998-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 75 [patent_no_of_words] => 11499 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365438.pdf [firstpage_image] =>[orig_patent_app_number] => 09194735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/194735
Process for manufacturing semiconductor package and circuit board assembly Dec 1, 1998 Issued
09/199600 METHOD FOR PHOTORESIST STRIP, SIDEWALL POLYMER REMOVAL AND PASSIVATION FOR ALUMINUM METALLIZATION Nov 24, 1998 Abandoned
Array ( [id] => 4234109 [patent_doc_number] => 06074934 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Apparatus for cleaving laser bars' [patent_app_type] => 1 [patent_app_number] => 9/196956 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1521 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074934.pdf [firstpage_image] =>[orig_patent_app_number] => 196956 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196956
Apparatus for cleaving laser bars Nov 19, 1998 Issued
Array ( [id] => 4348608 [patent_doc_number] => 06214728 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Method to encapsulate copper plug for interconnect metallization' [patent_app_type] => 1 [patent_app_number] => 9/196604 [patent_app_country] => US [patent_app_date] => 1998-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214728.pdf [firstpage_image] =>[orig_patent_app_number] => 196604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/196604
Method to encapsulate copper plug for interconnect metallization Nov 19, 1998 Issued
Array ( [id] => 1220460 [patent_doc_number] => 06703262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-09 [patent_title] => 'Method for planarizing circuit board and method for manufacturing semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/195514 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2911 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/703/06703262.pdf [firstpage_image] =>[orig_patent_app_number] => 09195514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195514
Method for planarizing circuit board and method for manufacturing semiconductor device Nov 18, 1998 Issued
Array ( [id] => 4152658 [patent_doc_number] => 06107114 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Process flow optimized to protect reflectance of silicon light valve' [patent_app_type] => 1 [patent_app_number] => 9/195406 [patent_app_country] => US [patent_app_date] => 1998-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 3696 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107114.pdf [firstpage_image] =>[orig_patent_app_number] => 195406 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/195406
Process flow optimized to protect reflectance of silicon light valve Nov 18, 1998 Issued
Array ( [id] => 4102141 [patent_doc_number] => 06100176 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Methods and structures for gold interconnections in integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/188970 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3357 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100176.pdf [firstpage_image] =>[orig_patent_app_number] => 188970 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188970
Methods and structures for gold interconnections in integrated circuits Nov 9, 1998 Issued
Array ( [id] => 4312830 [patent_doc_number] => 06242336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Semiconductor device having multilevel interconnection structure and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/186067 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 53 [patent_no_of_words] => 11852 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242336.pdf [firstpage_image] =>[orig_patent_app_number] => 186067 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/186067
Semiconductor device having multilevel interconnection structure and method for fabricating the same Nov 4, 1998 Issued
Array ( [id] => 1416318 [patent_doc_number] => 06518168 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Self-assembled monolayer directed patterning of surfaces' [patent_app_type] => B1 [patent_app_number] => 09/029317 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 12960 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518168.pdf [firstpage_image] =>[orig_patent_app_number] => 09029317 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/029317
Self-assembled monolayer directed patterning of surfaces Nov 1, 1998 Issued
Array ( [id] => 4301660 [patent_doc_number] => 06251717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Viable memory cell formed using rapid thermal annealing' [patent_app_type] => 1 [patent_app_number] => 9/163315 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6356 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251717.pdf [firstpage_image] =>[orig_patent_app_number] => 163315 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163315
Viable memory cell formed using rapid thermal annealing Sep 29, 1998 Issued
Array ( [id] => 4359237 [patent_doc_number] => 06169024 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Process to manufacture continuous metal interconnects' [patent_app_type] => 1 [patent_app_number] => 9/163847 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2560 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169024.pdf [firstpage_image] =>[orig_patent_app_number] => 163847 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163847
Process to manufacture continuous metal interconnects Sep 29, 1998 Issued
Array ( [id] => 4408216 [patent_doc_number] => 06309936 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Integrated formation of LDD and non-LDD semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 9/163965 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 33 [patent_no_of_words] => 6727 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/309/06309936.pdf [firstpage_image] =>[orig_patent_app_number] => 163965 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/163965
Integrated formation of LDD and non-LDD semiconductor devices Sep 29, 1998 Issued
Array ( [id] => 4394881 [patent_doc_number] => 06297113 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby' [patent_app_type] => 1 [patent_app_number] => 9/161745 [patent_app_country] => US [patent_app_date] => 1998-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 7958 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/297/06297113.pdf [firstpage_image] =>[orig_patent_app_number] => 161745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/161745
Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby Sep 28, 1998 Issued
Array ( [id] => 4293509 [patent_doc_number] => 06197634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Rugged metal electrodes for metal-insulator-metal capacitors' [patent_app_type] => 1 [patent_app_number] => 9/161156 [patent_app_country] => US [patent_app_date] => 1998-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2509 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197634.pdf [firstpage_image] =>[orig_patent_app_number] => 161156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/161156
Rugged metal electrodes for metal-insulator-metal capacitors Sep 24, 1998 Issued
Array ( [id] => 4084043 [patent_doc_number] => 06162696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Method of fabricating a feature in an integrated circuit using a two mask process with a single edge definition layer' [patent_app_type] => 1 [patent_app_number] => 9/160012 [patent_app_country] => US [patent_app_date] => 1998-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 51 [patent_no_of_words] => 6393 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162696.pdf [firstpage_image] =>[orig_patent_app_number] => 160012 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/160012
Method of fabricating a feature in an integrated circuit using a two mask process with a single edge definition layer Sep 23, 1998 Issued
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