Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4369370 [patent_doc_number] => 06287964 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Method for forming a metallization layer of a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/158794 [patent_app_country] => US [patent_app_date] => 1998-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3015 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/287/06287964.pdf [firstpage_image] =>[orig_patent_app_number] => 158794 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/158794
Method for forming a metallization layer of a semiconductor device Sep 22, 1998 Issued
Array ( [id] => 4188893 [patent_doc_number] => 06153515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method of forming multilayered film' [patent_app_type] => 1 [patent_app_number] => 9/156896 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4867 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153515.pdf [firstpage_image] =>[orig_patent_app_number] => 156896 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/156896
Method of forming multilayered film Sep 17, 1998 Issued
Array ( [id] => 4420542 [patent_doc_number] => 06225209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Method of fabricating crack resistant inter-layer dielectric for a salicide process' [patent_app_type] => 1 [patent_app_number] => 9/150525 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1677 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225209.pdf [firstpage_image] =>[orig_patent_app_number] => 150525 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150525
Method of fabricating crack resistant inter-layer dielectric for a salicide process Sep 9, 1998 Issued
Array ( [id] => 4083766 [patent_doc_number] => 06162677 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Semiconductor device fabricating method' [patent_app_type] => 1 [patent_app_number] => 9/151355 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 64 [patent_no_of_words] => 11055 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/162/06162677.pdf [firstpage_image] =>[orig_patent_app_number] => 151355 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/151355
Semiconductor device fabricating method Sep 9, 1998 Issued
Array ( [id] => 4098111 [patent_doc_number] => 06048787 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Borderless contacts for dual-damascene interconnect process' [patent_app_type] => 1 [patent_app_number] => 9/149266 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 22 [patent_no_of_words] => 1583 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/048/06048787.pdf [firstpage_image] =>[orig_patent_app_number] => 149266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149266
Borderless contacts for dual-damascene interconnect process Sep 7, 1998 Issued
Array ( [id] => 4405842 [patent_doc_number] => 06171913 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Process for manufacturing a single asymmetric pocket implant' [patent_app_type] => 1 [patent_app_number] => 9/149256 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1700 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171913.pdf [firstpage_image] =>[orig_patent_app_number] => 149256 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149256
Process for manufacturing a single asymmetric pocket implant Sep 7, 1998 Issued
Array ( [id] => 1379270 [patent_doc_number] => 06555455 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Methods of passivating an oxide surface subjected to a conductive material anneal' [patent_app_type] => B1 [patent_app_number] => 09/146296 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 5884 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/555/06555455.pdf [firstpage_image] =>[orig_patent_app_number] => 09146296 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146296
Methods of passivating an oxide surface subjected to a conductive material anneal Sep 2, 1998 Issued
Array ( [id] => 4312321 [patent_doc_number] => 06242302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 9/146840 [patent_app_country] => US [patent_app_date] => 1998-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2322 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242302.pdf [firstpage_image] =>[orig_patent_app_number] => 146840 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/146840
Semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry Sep 2, 1998 Issued
Array ( [id] => 4366772 [patent_doc_number] => 06274486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Metal contact and process' [patent_app_type] => 1 [patent_app_number] => 9/145437 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4505 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274486.pdf [firstpage_image] =>[orig_patent_app_number] => 145437 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145437
Metal contact and process Sep 1, 1998 Issued
Array ( [id] => 4102976 [patent_doc_number] => 06051508 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Manufacturing method of semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/145464 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 18 [patent_no_of_words] => 5086 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/051/06051508.pdf [firstpage_image] =>[orig_patent_app_number] => 145464 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/145464
Manufacturing method of semiconductor device Sep 1, 1998 Issued
Array ( [id] => 4122744 [patent_doc_number] => 06127089 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques' [patent_app_type] => 1 [patent_app_number] => 9/143105 [patent_app_country] => US [patent_app_date] => 1998-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 23 [patent_no_of_words] => 4464 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127089.pdf [firstpage_image] =>[orig_patent_app_number] => 143105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/143105
Interconnect structure with low k dielectric materials and method of making the same with single and dual damascene techniques Aug 27, 1998 Issued
Array ( [id] => 4292336 [patent_doc_number] => 06180484 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Chemical plasma treatment for rounding tungsten surface spires' [patent_app_type] => 1 [patent_app_number] => 9/140776 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2204 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180484.pdf [firstpage_image] =>[orig_patent_app_number] => 140776 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140776
Chemical plasma treatment for rounding tungsten surface spires Aug 25, 1998 Issued
Array ( [id] => 4107914 [patent_doc_number] => 06057228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Method of forming interconnection for semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/140834 [patent_app_country] => US [patent_app_date] => 1998-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1412 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057228.pdf [firstpage_image] =>[orig_patent_app_number] => 140834 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/140834
Method of forming interconnection for semiconductor device Aug 25, 1998 Issued
Array ( [id] => 4234953 [patent_doc_number] => 06165829 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Thin film transistor and fabrication method therefor' [patent_app_type] => 1 [patent_app_number] => 9/139266 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 1778 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165829.pdf [firstpage_image] =>[orig_patent_app_number] => 139266 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/139266
Thin film transistor and fabrication method therefor Aug 24, 1998 Issued
Array ( [id] => 4125615 [patent_doc_number] => 06127276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Method of formation for a via opening' [patent_app_type] => 1 [patent_app_number] => 9/138494 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1857 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127276.pdf [firstpage_image] =>[orig_patent_app_number] => 138494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/138494
Method of formation for a via opening Aug 23, 1998 Issued
Array ( [id] => 4366674 [patent_doc_number] => 06274479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Flowable germanium doped silicate glass for use as a spacer oxide' [patent_app_type] => 1 [patent_app_number] => 9/137736 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3266 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/274/06274479.pdf [firstpage_image] =>[orig_patent_app_number] => 137736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137736
Flowable germanium doped silicate glass for use as a spacer oxide Aug 20, 1998 Issued
Array ( [id] => 4258916 [patent_doc_number] => 06204166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for forming dual damascene structures' [patent_app_type] => 1 [patent_app_number] => 9/137525 [patent_app_country] => US [patent_app_date] => 1998-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2382 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204166.pdf [firstpage_image] =>[orig_patent_app_number] => 137525 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/137525
Method for forming dual damascene structures Aug 20, 1998 Issued
Array ( [id] => 4290272 [patent_doc_number] => 06235630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Silicide pattern structures and methods of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/136384 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 32 [patent_no_of_words] => 3878 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235630.pdf [firstpage_image] =>[orig_patent_app_number] => 136384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136384
Silicide pattern structures and methods of fabricating the same Aug 18, 1998 Issued
Array ( [id] => 4139006 [patent_doc_number] => 06060344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method for producing a semiconductor substrate' [patent_app_type] => 1 [patent_app_number] => 9/136294 [patent_app_country] => US [patent_app_date] => 1998-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 33 [patent_no_of_words] => 7465 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060344.pdf [firstpage_image] =>[orig_patent_app_number] => 136294 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/136294
Method for producing a semiconductor substrate Aug 18, 1998 Issued
Array ( [id] => 4116292 [patent_doc_number] => 06071751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Deuterium sintering with rapid quenching' [patent_app_type] => 1 [patent_app_number] => 9/123265 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2989 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/071/06071751.pdf [firstpage_image] =>[orig_patent_app_number] => 123265 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123265
Deuterium sintering with rapid quenching Jul 27, 1998 Issued
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