
Laura Mary Menz
Examiner (ID: 16260)
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813 |
| Total Applications | 2273 |
| Issued Applications | 1951 |
| Pending Applications | 152 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17963701
[patent_doc_number] => 20220344282
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => STRESS AND OVERLAY MANAGEMENT FOR SEMICONDUCTOR PROCESSING
[patent_app_type] => utility
[patent_app_number] => 17/730527
[patent_app_country] => US
[patent_app_date] => 2022-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3572
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 19
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17730527
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/730527 | Stress and overlay management for semiconductor processing | Apr 26, 2022 | Issued |
Array
(
[id] => 17780363
[patent_doc_number] => 20220246713
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => DISPLAY APPARATUS
[patent_app_type] => utility
[patent_app_number] => 17/728474
[patent_app_country] => US
[patent_app_date] => 2022-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10463
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17728474
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/728474 | Display apparatus | Apr 24, 2022 | Issued |
Array
(
[id] => 19356978
[patent_doc_number] => 12057435
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-06
[patent_title] => Semiconductor package
[patent_app_type] => utility
[patent_app_number] => 17/723981
[patent_app_country] => US
[patent_app_date] => 2022-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 11455
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723981
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/723981 | Semiconductor package | Apr 18, 2022 | Issued |
Array
(
[id] => 19720102
[patent_doc_number] => 12205645
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-21
[patent_title] => Three-dimensional memory structure fabrication using channel replacement
[patent_app_type] => utility
[patent_app_number] => 17/723204
[patent_app_country] => US
[patent_app_date] => 2022-04-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 50
[patent_no_of_words] => 8625
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17723204
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/723204 | Three-dimensional memory structure fabrication using channel replacement | Apr 17, 2022 | Issued |
Array
(
[id] => 18593447
[patent_doc_number] => 11742359
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-29
[patent_title] => Electronic device
[patent_app_type] => utility
[patent_app_number] => 17/721297
[patent_app_country] => US
[patent_app_date] => 2022-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 8007
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17721297
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/721297 | Electronic device | Apr 13, 2022 | Issued |
Array
(
[id] => 19935139
[patent_doc_number] => 12308347
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-05-20
[patent_title] => Interconnected stacked circuits
[patent_app_type] => utility
[patent_app_number] => 17/718145
[patent_app_country] => US
[patent_app_date] => 2022-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 0
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 16
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718145
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/718145 | Interconnected stacked circuits | Apr 10, 2022 | Issued |
Array
(
[id] => 17764906
[patent_doc_number] => 20220238519
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-28
[patent_title] => Semiconductor Devices Having Gate Dielectric Layers of Varying Thicknesses and Methods of Forming the Same
[patent_app_type] => utility
[patent_app_number] => 17/717296
[patent_app_country] => US
[patent_app_date] => 2022-04-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9158
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17717296
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/717296 | Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same | Apr 10, 2022 | Issued |
Array
(
[id] => 19912515
[patent_doc_number] => 12288734
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-29
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 17/714202
[patent_app_country] => US
[patent_app_date] => 2022-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 25
[patent_no_of_words] => 4337
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714202
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/714202 | Semiconductor device | Apr 5, 2022 | Issued |
Array
(
[id] => 19199087
[patent_doc_number] => 11996336
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-28
[patent_title] => Electron beam probing techniques and related structures
[patent_app_type] => utility
[patent_app_number] => 17/714770
[patent_app_country] => US
[patent_app_date] => 2022-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 24
[patent_no_of_words] => 17131
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17714770
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/714770 | Electron beam probing techniques and related structures | Apr 5, 2022 | Issued |
Array
(
[id] => 18679903
[patent_doc_number] => 20230317561
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => SCALABLE ARCHITECTURE FOR MULTI-DIE SEMICONDUCTOR PACKAGES
[patent_app_type] => utility
[patent_app_number] => 17/708417
[patent_app_country] => US
[patent_app_date] => 2022-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6649
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17708417
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/708417 | SCALABLE ARCHITECTURE FOR MULTI-DIE SEMICONDUCTOR PACKAGES | Mar 29, 2022 | Pending |
Array
(
[id] => 19828841
[patent_doc_number] => 12249637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-11
[patent_title] => Semiconductor integrated circuit device
[patent_app_type] => utility
[patent_app_number] => 17/706177
[patent_app_country] => US
[patent_app_date] => 2022-03-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 8067
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 297
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17706177
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/706177 | Semiconductor integrated circuit device | Mar 27, 2022 | Issued |
Array
(
[id] => 18658743
[patent_doc_number] => 20230304741
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => Magnetic Annealing Equipment and Method
[patent_app_type] => utility
[patent_app_number] => 17/656588
[patent_app_country] => US
[patent_app_date] => 2022-03-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9316
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17656588
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/656588 | Magnetic annealing equipment and method | Mar 24, 2022 | Issued |
Array
(
[id] => 19582597
[patent_doc_number] => 12148725
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-19
[patent_title] => Bonding structures and methods for forming the same
[patent_app_type] => utility
[patent_app_number] => 17/699048
[patent_app_country] => US
[patent_app_date] => 2022-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 6501
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17699048
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/699048 | Bonding structures and methods for forming the same | Mar 17, 2022 | Issued |
Array
(
[id] => 18653283
[patent_doc_number] => 20230299123
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => INDUCTORS FOR HYBRID BONDING INTERCONNECT ARCHITECTURES
[patent_app_type] => utility
[patent_app_number] => 17/698939
[patent_app_country] => US
[patent_app_date] => 2022-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10187
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698939
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/698939 | INDUCTORS FOR HYBRID BONDING INTERCONNECT ARCHITECTURES | Mar 17, 2022 | Pending |
Array
(
[id] => 18081076
[patent_doc_number] => 20220406688
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-22
[patent_title] => INTEGRATED CIRCUIT DEVICE INCLUDING A THROUGH-VIA STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/697049
[patent_app_country] => US
[patent_app_date] => 2022-03-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7688
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697049
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/697049 | Integrated circuit device including a through-via structure | Mar 16, 2022 | Issued |
Array
(
[id] => 18653335
[patent_doc_number] => 20230299175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => GATE SPACER AND FORMATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/696257
[patent_app_country] => US
[patent_app_date] => 2022-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7734
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696257
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/696257 | Gate spacer and formation method thereof | Mar 15, 2022 | Issued |
Array
(
[id] => 19894971
[patent_doc_number] => 20250120283
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-10
[patent_title] => LIGHT EMITTING DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/281864
[patent_app_country] => US
[patent_app_date] => 2022-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20220
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 12
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18281864
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/281864 | LIGHT EMITTING DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE | Mar 15, 2022 | Pending |
Array
(
[id] => 18653335
[patent_doc_number] => 20230299175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-21
[patent_title] => GATE SPACER AND FORMATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/696257
[patent_app_country] => US
[patent_app_date] => 2022-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7734
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 27
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17696257
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/696257 | Gate spacer and formation method thereof | Mar 15, 2022 | Issued |
Array
(
[id] => 19679184
[patent_doc_number] => 12191055
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-07
[patent_title] => Method for fabricating a micro resistance layer and method for fabricating a micro resistor
[patent_app_type] => utility
[patent_app_number] => 17/654818
[patent_app_country] => US
[patent_app_date] => 2022-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 5732
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17654818
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/654818 | Method for fabricating a micro resistance layer and method for fabricating a micro resistor | Mar 14, 2022 | Issued |
Array
(
[id] => 18564710
[patent_doc_number] => 11729980
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-15
[patent_title] => 3-dimensional NOR memory array architecture and methods for fabrication thereof
[patent_app_type] => utility
[patent_app_number] => 17/690943
[patent_app_country] => US
[patent_app_date] => 2022-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 60
[patent_figures_cnt] => 63
[patent_no_of_words] => 14737
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 281
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690943
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/690943 | 3-dimensional NOR memory array architecture and methods for fabrication thereof | Mar 8, 2022 | Issued |