Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18350852 [patent_doc_number] => 20230138963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-04 [patent_title] => SEMICONDUCTOR DEVICE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/514507 [patent_app_country] => US [patent_app_date] => 2021-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17514507 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/514507
Semiconductor device structure Oct 28, 2021 Issued
Array ( [id] => 18337036 [patent_doc_number] => 20230128985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => EARLY BACKSIDE FIRST POWER DELIVERY NETWORK [patent_app_type] => utility [patent_app_number] => 17/508113 [patent_app_country] => US [patent_app_date] => 2021-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4881 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508113 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/508113
Early backside first power delivery network Oct 21, 2021 Issued
Array ( [id] => 18913061 [patent_doc_number] => 11876048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Memory device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 17/504546 [patent_app_country] => US [patent_app_date] => 2021-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 34 [patent_no_of_words] => 4749 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17504546 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/504546
Memory device and method of manufacturing the same Oct 18, 2021 Issued
Array ( [id] => 17871013 [patent_doc_number] => 20220293750 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-15 [patent_title] => INTEGRATED CIRCUIT INCLUDING BACKSIDE CONDUCTIVE VIAS [patent_app_type] => utility [patent_app_number] => 17/501852 [patent_app_country] => US [patent_app_date] => 2021-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12092 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17501852 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/501852
Integrated circuit including backside conductive vias Oct 13, 2021 Issued
Array ( [id] => 19460127 [patent_doc_number] => 12100634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Semiconductor device with re-fill layer [patent_app_type] => utility [patent_app_number] => 17/500026 [patent_app_country] => US [patent_app_date] => 2021-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9988 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17500026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/500026
Semiconductor device with re-fill layer Oct 12, 2021 Issued
Array ( [id] => 17373731 [patent_doc_number] => 20220028783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => TOP VIA STACK [patent_app_type] => utility [patent_app_number] => 17/496252 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4505 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17496252 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/496252
Top via stack Oct 6, 2021 Issued
Array ( [id] => 18528925 [patent_doc_number] => 11715931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-01 [patent_title] => Strained and strain control regions in optical devices [patent_app_type] => utility [patent_app_number] => 17/495378 [patent_app_country] => US [patent_app_date] => 2021-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 18215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495378 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495378
Strained and strain control regions in optical devices Oct 5, 2021 Issued
Array ( [id] => 18840189 [patent_doc_number] => 11848269 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Techniques to create power connections from floating nets in standard cells [patent_app_type] => utility [patent_app_number] => 17/493574 [patent_app_country] => US [patent_app_date] => 2021-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3898 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17493574 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/493574
Techniques to create power connections from floating nets in standard cells Oct 3, 2021 Issued
Array ( [id] => 18874734 [patent_doc_number] => 11862557 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Selectable monolithic or external scalable die-to-die interconnection system methodology [patent_app_type] => utility [patent_app_number] => 17/483535 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 10857 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483535
Selectable monolithic or external scalable die-to-die interconnection system methodology Sep 22, 2021 Issued
Array ( [id] => 17339381 [patent_doc_number] => 20220005712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => Substrate Processing Apparatus, Method of Manufacturing Semiconductor Device and Method of Processing Substrate Support [patent_app_type] => utility [patent_app_number] => 17/477079 [patent_app_country] => US [patent_app_date] => 2021-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9129 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477079 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477079
Substrate processing apparatus, method of manufacturing semiconductor device and method of processing substrate support Sep 15, 2021 Issued
Array ( [id] => 18254914 [patent_doc_number] => 20230081953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => DECOUPLED INTERCONNECT STRUCTURES [patent_app_type] => utility [patent_app_number] => 17/447586 [patent_app_country] => US [patent_app_date] => 2021-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447586 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447586
Decoupled interconnect structures Sep 13, 2021 Issued
Array ( [id] => 17359948 [patent_doc_number] => 20220020744 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-20 [patent_title] => HIGH PERFORMANCE NANOSHEET FABRICATION METHOD WITH ENHANCED HIGH MOBILITY CHANNEL ELEMENTS [patent_app_type] => utility [patent_app_number] => 17/447506 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 336 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447506
High performance nanosheet fabrication method with enhanced high mobility channel elements Sep 12, 2021 Issued
Array ( [id] => 20386730 [patent_doc_number] => 12486448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-02 [patent_title] => Perovskite compound-based electroluminescent layer and light emitting device comprising same [patent_app_type] => utility [patent_app_number] => 18/044839 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3375 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18044839 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/044839
Perovskite compound-based electroluminescent layer and light emitting device comprising same Sep 9, 2021 Issued
Array ( [id] => 18874786 [patent_doc_number] => 11862609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Semiconductor die including fuse structure and methods for forming the same [patent_app_type] => utility [patent_app_number] => 17/472115 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6250 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472115 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472115
Semiconductor die including fuse structure and methods for forming the same Sep 9, 2021 Issued
Array ( [id] => 19796312 [patent_doc_number] => 12237281 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-25 [patent_title] => Electronic package and implantable medical device including same [patent_app_type] => utility [patent_app_number] => 17/469098 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 9072 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469098 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469098
Electronic package and implantable medical device including same Sep 7, 2021 Issued
Array ( [id] => 17318954 [patent_doc_number] => 20210408004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/469340 [patent_app_country] => US [patent_app_date] => 2021-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17469340 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/469340
Semiconductor device and method of fabricating the same Sep 7, 2021 Issued
Array ( [id] => 18241870 [patent_doc_number] => 20230074181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => LOW COST EMBEDDED INTEGRATED CIRCUIT DIES [patent_app_type] => utility [patent_app_number] => 17/467666 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15183 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467666 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467666
Low cost embedded integrated circuit dies Sep 6, 2021 Issued
Array ( [id] => 19370533 [patent_doc_number] => 12062627 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-13 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 17/467964 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 8343 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467964
Semiconductor device Sep 6, 2021 Issued
Array ( [id] => 18048018 [patent_doc_number] => 11521976 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Semiconductor device with bit line contact and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 17/466102 [patent_app_country] => US [patent_app_date] => 2021-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 11075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17466102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/466102
Semiconductor device with bit line contact and method for fabricating the same Sep 2, 2021 Issued
Array ( [id] => 19244542 [patent_doc_number] => 12014997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Dummy stacked structures surrounding TSVs and method forming the same [patent_app_type] => utility [patent_app_number] => 17/464903 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 28 [patent_no_of_words] => 7643 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464903
Dummy stacked structures surrounding TSVs and method forming the same Sep 1, 2021 Issued
Menu