
Laura Mary Menz
Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813 |
| Total Applications | 2324 |
| Issued Applications | 1995 |
| Pending Applications | 138 |
| Abandoned Applications | 216 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19229652
[patent_doc_number] => 12009296
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-11
[patent_title] => Semiconductor device and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/461924
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4223
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461924
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/461924 | Semiconductor device and manufacturing method thereof | Aug 29, 2021 | Issued |
Array
(
[id] => 18464412
[patent_doc_number] => 11688708
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-27
[patent_title] => Chip structure and method for forming the same
[patent_app_type] => utility
[patent_app_number] => 17/460937
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 7940
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460937
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460937 | Chip structure and method for forming the same | Aug 29, 2021 | Issued |
Array
(
[id] => 17448288
[patent_doc_number] => 20220068793
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-03
[patent_title] => SEMICONDUCTOR DEVICE FORMED ON SOI SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 17/460998
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3545
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460998
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/460998 | Semiconductor device formed on SOI substrate | Aug 29, 2021 | Issued |
Array
(
[id] => 18223033
[patent_doc_number] => 20230062027
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => SEMICONDUCTOR DIE INCLUDING GUARD RING STRUCTURE AND THREE-DIMENSIONAL DEVICE STRUCTURE INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/458687
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7601
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 117
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458687
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/458687 | Semiconductor die including guard ring structure and three-dimensional device structure including the same | Aug 26, 2021 | Issued |
Array
(
[id] => 18230321
[patent_doc_number] => 20230069315
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => THREE-DIMENSIONAL DEVICE STRUCTURE INCLUDING SUBSTRATE-EMBEDDED INTEGRATED PASSIVE DEVICE AND METHODS FOR MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/446053
[patent_app_country] => US
[patent_app_date] => 2021-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7683
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446053
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/446053 | Three-dimensional device structure including substrate-embedded integrated passive device and methods for making the same | Aug 25, 2021 | Issued |
Array
(
[id] => 17278127
[patent_doc_number] => 20210384325
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-09
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/411704
[patent_app_country] => US
[patent_app_date] => 2021-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14007
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17411704
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/411704 | Semiconductor device and method for manufacturing the same | Aug 24, 2021 | Issued |
Array
(
[id] => 18211014
[patent_doc_number] => 20230057276
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-23
[patent_title] => MIXED PITCH TRACK PATTERN
[patent_app_type] => utility
[patent_app_number] => 17/405860
[patent_app_country] => US
[patent_app_date] => 2021-08-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9472
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405860
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/405860 | Mixed pitch track pattern | Aug 17, 2021 | Issued |
Array
(
[id] => 17262790
[patent_doc_number] => 20210375775
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-02
[patent_title] => Fan-Out Package Having a Main Die and a Dummy Die
[patent_app_type] => utility
[patent_app_number] => 17/402734
[patent_app_country] => US
[patent_app_date] => 2021-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8656
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402734
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/402734 | Fan-out package having a main die and a dummy die | Aug 15, 2021 | Issued |
Array
(
[id] => 17263093
[patent_doc_number] => 20210376078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-02
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/402507
[patent_app_country] => US
[patent_app_date] => 2021-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7838
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402507
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/402507 | Semiconductor device and method of forming the semiconductor device | Aug 13, 2021 | Issued |
Array
(
[id] => 18757364
[patent_doc_number] => 20230360825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-09
[patent_title] => TEMPERATURE SENSOR AND METHOD FOR PRODUCING A TEMPERATURE SENSOR OF THIS KIND
[patent_app_type] => utility
[patent_app_number] => 18/042534
[patent_app_country] => US
[patent_app_date] => 2021-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8429
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18042534
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/042534 | Temperature sensor and method for producing a temperature sensor of this kind | Aug 11, 2021 | Issued |
Array
(
[id] => 17566651
[patent_doc_number] => 20220130800
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/399221
[patent_app_country] => US
[patent_app_date] => 2021-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4456
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399221
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/399221 | Semiconductor structure | Aug 10, 2021 | Issued |
Array
(
[id] => 17262745
[patent_doc_number] => 20210375730
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-02
[patent_title] => PACKAGE WITH DIES MOUNTED ON OPPOSING SURFACES OF A LEADFRAME
[patent_app_type] => utility
[patent_app_number] => 17/399018
[patent_app_country] => US
[patent_app_date] => 2021-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4484
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -8
[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17399018
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/399018 | Package with dies mounted on opposing surfaces of a leadframe | Aug 9, 2021 | Issued |
Array
(
[id] => 17247060
[patent_doc_number] => 20210366805
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-25
[patent_title] => SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/396565
[patent_app_country] => US
[patent_app_date] => 2021-08-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6472
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17396565
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/396565 | Semiconductor structure | Aug 5, 2021 | Issued |
Array
(
[id] => 18827647
[patent_doc_number] => 11842937
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-12
[patent_title] => Encapsulation stack for improved humidity performance and related fabrication methods
[patent_app_type] => utility
[patent_app_number] => 17/390020
[patent_app_country] => US
[patent_app_date] => 2021-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 23
[patent_no_of_words] => 13694
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390020
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/390020 | Encapsulation stack for improved humidity performance and related fabrication methods | Jul 29, 2021 | Issued |
Array
(
[id] => 17986086
[patent_doc_number] => 20220352123
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
[patent_app_type] => utility
[patent_app_number] => 17/388788
[patent_app_country] => US
[patent_app_date] => 2021-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12571
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 73
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388788
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/388788 | Semiconductor devices and methods of manufacture | Jul 28, 2021 | Issued |
Array
(
[id] => 19183803
[patent_doc_number] => 11990404
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-05-21
[patent_title] => Heat dissipation for semiconductor devices and methods of manufacture
[patent_app_type] => utility
[patent_app_number] => 17/381583
[patent_app_country] => US
[patent_app_date] => 2021-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 59
[patent_figures_cnt] => 86
[patent_no_of_words] => 16054
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381583
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/381583 | Heat dissipation for semiconductor devices and methods of manufacture | Jul 20, 2021 | Issued |
Array
(
[id] => 17217842
[patent_doc_number] => 20210351180
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-11
[patent_title] => METHOD OF MAKING MULTIPLE NANO LAYER TRANSISTORS TO ENHANCE A MULTIPLE STACK CFET PERFORMANCE
[patent_app_type] => utility
[patent_app_number] => 17/381384
[patent_app_country] => US
[patent_app_date] => 2021-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7185
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17381384
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/381384 | Method of making multiple nano layer transistors to enhance a multiple stack CFET performance | Jul 20, 2021 | Issued |
Array
(
[id] => 18047989
[patent_doc_number] => 11521947
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-12-06
[patent_title] => Space efficient flip chip joint design
[patent_app_type] => utility
[patent_app_number] => 17/376053
[patent_app_country] => US
[patent_app_date] => 2021-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 26
[patent_no_of_words] => 3628
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 141
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17376053
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/376053 | Space efficient flip chip joint design | Jul 13, 2021 | Issued |
Array
(
[id] => 17840789
[patent_doc_number] => 20220278095
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-01
[patent_title] => STACKED SEMICONDUCTOR DEVICE AND METHOD
[patent_app_type] => utility
[patent_app_number] => 17/371660
[patent_app_country] => US
[patent_app_date] => 2021-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16556
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371660
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/371660 | Stacked semiconductor device and method | Jul 8, 2021 | Issued |
Array
(
[id] => 18175188
[patent_doc_number] => 11574905
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-07
[patent_title] => Resistor with doped regions and semiconductor devices having the same
[patent_app_type] => utility
[patent_app_number] => 17/371494
[patent_app_country] => US
[patent_app_date] => 2021-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 41
[patent_no_of_words] => 5177
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17371494
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/371494 | Resistor with doped regions and semiconductor devices having the same | Jul 8, 2021 | Issued |