Search

Laura Mary Menz

Examiner (ID: 16260)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2273
Issued Applications
1951
Pending Applications
152
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17566587 [patent_doc_number] => 20220130736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => CONDUCTIVE FEATURE WITH NON-UNIFORM CRITICAL DIMENSION AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/077842 [patent_app_country] => US [patent_app_date] => 2020-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8329 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17077842 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/077842
Conductive feature with non-uniform critical dimension and method of manufacturing the same Oct 21, 2020 Issued
Array ( [id] => 17536761 [patent_doc_number] => 20220115370 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR DEVICE WITH SHORT-RESISTANT CAPACITOR PLATE [patent_app_type] => utility [patent_app_number] => 17/069365 [patent_app_country] => US [patent_app_date] => 2020-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17069365 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/069365
Semiconductor device with short-resistant capacitor plate Oct 12, 2020 Issued
Array ( [id] => 18263103 [patent_doc_number] => 11610812 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Multi-wafer capping layer for metal arcing protection [patent_app_type] => utility [patent_app_number] => 17/038198 [patent_app_country] => US [patent_app_date] => 2020-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 6735 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17038198 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/038198
Multi-wafer capping layer for metal arcing protection Sep 29, 2020 Issued
Array ( [id] => 17971404 [patent_doc_number] => 11488953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Semiconductor device having gate isolation layer [patent_app_type] => utility [patent_app_number] => 17/036355 [patent_app_country] => US [patent_app_date] => 2020-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 35 [patent_no_of_words] => 10389 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036355 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/036355
Semiconductor device having gate isolation layer Sep 28, 2020 Issued
Array ( [id] => 17486859 [patent_doc_number] => 20220094363 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => MULTIBIT MULTI-HEIGHT CELL TO IMPROVE PIN ACCESSIBILITY [patent_app_type] => utility [patent_app_number] => 17/030087 [patent_app_country] => US [patent_app_date] => 2020-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030087 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/030087
Multibit multi-height cell to improve pin accessibility Sep 22, 2020 Issued
Array ( [id] => 18175333 [patent_doc_number] => 11575052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Semiconductor device and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/014607 [patent_app_country] => US [patent_app_date] => 2020-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 10105 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17014607 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/014607
Semiconductor device and method of forming the same Sep 7, 2020 Issued
Array ( [id] => 16528769 [patent_doc_number] => 20200402850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-24 [patent_title] => WIRING CIRCUIT AND METHOD FOR PRODUCING SAME [patent_app_type] => utility [patent_app_number] => 17/013055 [patent_app_country] => US [patent_app_date] => 2020-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17013055 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/013055
Wiring circuit and method for producing same Sep 3, 2020 Issued
Array ( [id] => 17544197 [patent_doc_number] => 11309331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-19 [patent_title] => 3-dimensional NOR memory array architecture and methods for fabrication thereof [patent_app_type] => utility [patent_app_number] => 17/011836 [patent_app_country] => US [patent_app_date] => 2020-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 63 [patent_no_of_words] => 14706 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17011836 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/011836
3-dimensional NOR memory array architecture and methods for fabrication thereof Sep 2, 2020 Issued
Array ( [id] => 16512737 [patent_doc_number] => 20200391995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-17 [patent_title] => METHODS FOR PACKAGING A MICROELECTROMECHANICAL SYSTEMS DEVICE [patent_app_type] => utility [patent_app_number] => 17/006906 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17006906 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/006906
Methods for packaging a microelectromechanical systems device Aug 30, 2020 Issued
Array ( [id] => 18131315 [patent_doc_number] => 11557532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure [patent_app_type] => utility [patent_app_number] => 17/007821 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 8400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007821 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007821
Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure Aug 30, 2020 Issued
Array ( [id] => 17818641 [patent_doc_number] => 11424265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same [patent_app_type] => utility [patent_app_number] => 17/004811 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16123 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004811 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004811
Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same Aug 26, 2020 Issued
Array ( [id] => 17787788 [patent_doc_number] => 11410924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Three-dimensional memory device including contact via structures for multi-level stepped surfaces and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/999388 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 62 [patent_no_of_words] => 20212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999388 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999388
Three-dimensional memory device including contact via structures for multi-level stepped surfaces and methods for forming the same Aug 20, 2020 Issued
Array ( [id] => 19875128 [patent_doc_number] => 12268014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Resistors for integrated circuits [patent_app_type] => utility [patent_app_number] => 17/636108 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 28 [patent_no_of_words] => 8274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17636108 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/636108
Resistors for integrated circuits Aug 18, 2020 Issued
Array ( [id] => 16904804 [patent_doc_number] => 20210183720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MICRO HEATER CHIP, WAFER-LEVEL ELECTRONIC CHIP ASSEMBLY AND CHIP ASSEMBLY STACKING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/997191 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997191 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997191
Micro heater chip, wafer-level electronic chip assembly and chip assembly stacking system Aug 18, 2020 Issued
Array ( [id] => 16487783 [patent_doc_number] => 20200381392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => Tri-Layer CoWoS Structure [patent_app_type] => utility [patent_app_number] => 16/995080 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16995080 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/995080
Tri-layer CoWoS structure Aug 16, 2020 Issued
Array ( [id] => 17410156 [patent_doc_number] => 11251053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Process for producing an electrode in a base substrate and electronic device [patent_app_type] => utility [patent_app_number] => 16/990556 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2061 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990556
Process for producing an electrode in a base substrate and electronic device Aug 10, 2020 Issued
Array ( [id] => 17590795 [patent_doc_number] => 11329072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Electronic device [patent_app_type] => utility [patent_app_number] => 16/944171 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16944171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/944171
Electronic device Jul 30, 2020 Issued
Array ( [id] => 16440554 [patent_doc_number] => 20200357881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => FINGERED CAPACITOR WITH LOW-K AND ULTRA-LOW-K DIELECTRIC LAYERS [patent_app_type] => utility [patent_app_number] => 16/941654 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941654 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941654
Fingered capacitor with low-k and ultra-low-k dielectric layers Jul 28, 2020 Issued
Array ( [id] => 16440595 [patent_doc_number] => 20200357922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => Multi-Layer Film Device and Method [patent_app_type] => utility [patent_app_number] => 16/939199 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939199
Multi-layer film device and method Jul 26, 2020 Issued
Array ( [id] => 17908592 [patent_doc_number] => 11462453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Semiconductor device with protection layers and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/926281 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8118 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926281
Semiconductor device with protection layers and method for fabricating the same Jul 9, 2020 Issued
Menu