Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18131315 [patent_doc_number] => 11557532 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-17 [patent_title] => Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure [patent_app_type] => utility [patent_app_number] => 17/007821 [patent_app_country] => US [patent_app_date] => 2020-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 20 [patent_no_of_words] => 8400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17007821 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/007821
Monolithic 3D integration inter-tier vias insertion scheme and associated layout structure Aug 30, 2020 Issued
Array ( [id] => 17818641 [patent_doc_number] => 11424265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same [patent_app_type] => utility [patent_app_number] => 17/004811 [patent_app_country] => US [patent_app_date] => 2020-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 16123 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17004811 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/004811
Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same Aug 26, 2020 Issued
Array ( [id] => 17787788 [patent_doc_number] => 11410924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Three-dimensional memory device including contact via structures for multi-level stepped surfaces and methods for forming the same [patent_app_type] => utility [patent_app_number] => 16/999388 [patent_app_country] => US [patent_app_date] => 2020-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 62 [patent_no_of_words] => 20212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16999388 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/999388
Three-dimensional memory device including contact via structures for multi-level stepped surfaces and methods for forming the same Aug 20, 2020 Issued
Array ( [id] => 19875128 [patent_doc_number] => 12268014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-01 [patent_title] => Resistors for integrated circuits [patent_app_type] => utility [patent_app_number] => 17/636108 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 28 [patent_no_of_words] => 8274 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17636108 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/636108
Resistors for integrated circuits Aug 18, 2020 Issued
Array ( [id] => 16904804 [patent_doc_number] => 20210183720 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => MICRO HEATER CHIP, WAFER-LEVEL ELECTRONIC CHIP ASSEMBLY AND CHIP ASSEMBLY STACKING SYSTEM [patent_app_type] => utility [patent_app_number] => 16/997191 [patent_app_country] => US [patent_app_date] => 2020-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16997191 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/997191
Micro heater chip, wafer-level electronic chip assembly and chip assembly stacking system Aug 18, 2020 Issued
Array ( [id] => 16487783 [patent_doc_number] => 20200381392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-12-03 [patent_title] => Tri-Layer CoWoS Structure [patent_app_type] => utility [patent_app_number] => 16/995080 [patent_app_country] => US [patent_app_date] => 2020-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16995080 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/995080
Tri-layer CoWoS structure Aug 16, 2020 Issued
Array ( [id] => 17410156 [patent_doc_number] => 11251053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Process for producing an electrode in a base substrate and electronic device [patent_app_type] => utility [patent_app_number] => 16/990556 [patent_app_country] => US [patent_app_date] => 2020-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2061 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16990556 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/990556
Process for producing an electrode in a base substrate and electronic device Aug 10, 2020 Issued
Array ( [id] => 17590795 [patent_doc_number] => 11329072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-10 [patent_title] => Electronic device [patent_app_type] => utility [patent_app_number] => 16/944171 [patent_app_country] => US [patent_app_date] => 2020-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16944171 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/944171
Electronic device Jul 30, 2020 Issued
Array ( [id] => 16440554 [patent_doc_number] => 20200357881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => FINGERED CAPACITOR WITH LOW-K AND ULTRA-LOW-K DIELECTRIC LAYERS [patent_app_type] => utility [patent_app_number] => 16/941654 [patent_app_country] => US [patent_app_date] => 2020-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3543 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16941654 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/941654
Fingered capacitor with low-k and ultra-low-k dielectric layers Jul 28, 2020 Issued
Array ( [id] => 16440595 [patent_doc_number] => 20200357922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-12 [patent_title] => Multi-Layer Film Device and Method [patent_app_type] => utility [patent_app_number] => 16/939199 [patent_app_country] => US [patent_app_date] => 2020-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16939199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/939199
Multi-layer film device and method Jul 26, 2020 Issued
Array ( [id] => 17908592 [patent_doc_number] => 11462453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-04 [patent_title] => Semiconductor device with protection layers and method for fabricating the same [patent_app_type] => utility [patent_app_number] => 16/926281 [patent_app_country] => US [patent_app_date] => 2020-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8118 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16926281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/926281
Semiconductor device with protection layers and method for fabricating the same Jul 9, 2020 Issued
Array ( [id] => 19425355 [patent_doc_number] => 12084758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Method of making graphene structures and devices [patent_app_type] => utility [patent_app_number] => 17/625016 [patent_app_country] => US [patent_app_date] => 2020-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 8714 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17625016 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/625016
Method of making graphene structures and devices Jul 6, 2020 Issued
Array ( [id] => 17353294 [patent_doc_number] => 11227941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Bipolar transistor and method for producing the same [patent_app_type] => utility [patent_app_number] => 16/920324 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6358 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920324 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/920324
Bipolar transistor and method for producing the same Jul 1, 2020 Issued
Array ( [id] => 16617249 [patent_doc_number] => 20210035902 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-02-04 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/919670 [patent_app_country] => US [patent_app_date] => 2020-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16919670 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/919670
Semiconductor device Jul 1, 2020 Issued
Array ( [id] => 17381220 [patent_doc_number] => 11239253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-01 [patent_title] => Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same [patent_app_type] => utility [patent_app_number] => 16/917597 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 71 [patent_no_of_words] => 24031 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917597 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917597
Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same Jun 29, 2020 Issued
Array ( [id] => 17818607 [patent_doc_number] => 11424231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same [patent_app_type] => utility [patent_app_number] => 16/917526 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 71 [patent_no_of_words] => 24031 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917526 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917526
Three-dimensional memory device having an epitaxial vertical semiconductor channel and method for making the same Jun 29, 2020 Issued
Array ( [id] => 17700237 [patent_doc_number] => 11373971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-28 [patent_title] => Semiconductor device structure and methods of forming the same [patent_app_type] => utility [patent_app_number] => 16/917640 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7803 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16917640 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/917640
Semiconductor device structure and methods of forming the same Jun 29, 2020 Issued
Array ( [id] => 17318894 [patent_doc_number] => 20210407944 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => SEMICONDUCTOR DEVICE ASSEMBLY WITH SACRIFICIAL PILLARS AND METHODS OF MANUFACTURING SACRIFICIAL PILLARS [patent_app_type] => utility [patent_app_number] => 16/916325 [patent_app_country] => US [patent_app_date] => 2020-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16916325 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/916325
Semiconductor device assembly with sacrificial pillars and methods of manufacturing sacrificial pillars Jun 29, 2020 Issued
Array ( [id] => 17318850 [patent_doc_number] => 20210407900 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => BACKSIDE CONNECTION STRUCTURES FOR NANOSTRUCTURES AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 16/910453 [patent_app_country] => US [patent_app_date] => 2020-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16805 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910453 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/910453
Backside connection structures for nanostructures and methods of forming the same Jun 23, 2020 Issued
Array ( [id] => 16364615 [patent_doc_number] => 20200321366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-10-08 [patent_title] => IMAGING DEVICE, IMAGING SYSTEM, AND MOVING BODY [patent_app_type] => utility [patent_app_number] => 16/909786 [patent_app_country] => US [patent_app_date] => 2020-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10198 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16909786 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/909786
Imaging device, imaging system, and moving body Jun 22, 2020 Issued
Menu