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Laura Mary Menz

Examiner (ID: 16260)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2273
Issued Applications
1951
Pending Applications
152
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15760251 [patent_doc_number] => 10622253 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Manufacturing method of semiconductor device [patent_app_type] => utility [patent_app_number] => 16/006739 [patent_app_country] => US [patent_app_date] => 2018-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4123 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16006739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/006739
Manufacturing method of semiconductor device Jun 11, 2018 Issued
Array ( [id] => 14843691 [patent_doc_number] => 20190280246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-12 [patent_title] => DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREFOR, AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/338165 [patent_app_country] => US [patent_app_date] => 2018-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9482 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16338165 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/338165
Display substrate and manufacturing method therefor, and display device Jun 6, 2018 Issued
Array ( [id] => 16638050 [patent_doc_number] => 10916565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => LTPS substrate and fabricating method thereof, thin film transistor thereof, array substrate thereof and display device thereof [patent_app_type] => utility [patent_app_number] => 16/330922 [patent_app_country] => US [patent_app_date] => 2018-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3605 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16330922 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/330922
LTPS substrate and fabricating method thereof, thin film transistor thereof, array substrate thereof and display device thereof May 14, 2018 Issued
Array ( [id] => 13421249 [patent_doc_number] => 20180262167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-13 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/976734 [patent_app_country] => US [patent_app_date] => 2018-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7483 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15976734 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/976734
Semiconductor device May 9, 2018 Issued
Array ( [id] => 15185103 [patent_doc_number] => 20190363143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => ORGANIC ELECTROLUMINESCENT DISPLAY PANEL AND DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 16/332876 [patent_app_country] => US [patent_app_date] => 2018-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16332876 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/332876
Organic electroluminescent display panel and display device May 2, 2018 Issued
Array ( [id] => 15185039 [patent_doc_number] => 20190363111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => METHOD FOR FABRICATING ARRAY SUBSTRATE MOTHERBOARD, ARRAY SUBSTRATE MOTHERBOARD AND DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 16/331766 [patent_app_country] => US [patent_app_date] => 2018-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16331766 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/331766
Method for fabricating array substrate motherboard, array substrate motherboard and detection method May 1, 2018 Issued
Array ( [id] => 13378519 [patent_doc_number] => 20180240801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE [patent_app_type] => utility [patent_app_number] => 15/960492 [patent_app_country] => US [patent_app_date] => 2018-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21003 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15960492 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/960492
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE Apr 22, 2018 Abandoned
Array ( [id] => 13392961 [patent_doc_number] => 20180248023 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-30 [patent_title] => BIPOLAR TRANSISTOR AND METHOD FOR PRODUCING THE SAME [patent_app_type] => utility [patent_app_number] => 15/957702 [patent_app_country] => US [patent_app_date] => 2018-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15957702 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/957702
Bipolar transistor and method for producing the same Apr 18, 2018 Issued
Array ( [id] => 13378421 [patent_doc_number] => 20180240752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => BEOL VERTICAL FUSE FORMED OVER AIR GAP [patent_app_type] => utility [patent_app_number] => 15/956355 [patent_app_country] => US [patent_app_date] => 2018-04-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6315 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15956355 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/956355
BEOL vertical fuse formed over air gap Apr 17, 2018 Issued
Array ( [id] => 14024573 [patent_doc_number] => 20190074280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-07 [patent_title] => METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 15/951194 [patent_app_country] => US [patent_app_date] => 2018-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15951194 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/951194
Method of manufacturing a semiconductor device Apr 11, 2018 Issued
Array ( [id] => 13349677 [patent_doc_number] => 20180226378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-09 [patent_title] => Three-Layer Package-on-Package Structure and Method Forming Same [patent_app_type] => utility [patent_app_number] => 15/942807 [patent_app_country] => US [patent_app_date] => 2018-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15942807 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/942807
Three-layer package-on-package structure and method forming same Apr 1, 2018 Issued
Array ( [id] => 13470189 [patent_doc_number] => 20180286637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => ION IMPLANTER AND ION IMPLANTATION METHOD [patent_app_type] => utility [patent_app_number] => 15/937346 [patent_app_country] => US [patent_app_date] => 2018-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6763 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15937346 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/937346
Ion implanter and ion implantation method Mar 26, 2018 Issued
Array ( [id] => 13435053 [patent_doc_number] => 20180269069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => Method of Manufacturing Semiconductor Device and Vacuum Processing Apparatus [patent_app_type] => utility [patent_app_number] => 15/919671 [patent_app_country] => US [patent_app_date] => 2018-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15919671 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/919671
Method of manufacturing semiconductor device and vacuum processing apparatus Mar 12, 2018 Issued
Array ( [id] => 13378367 [patent_doc_number] => 20180240725 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-08-23 [patent_title] => SEMICONDUCTOR CHIP, METHOD FOR MOUNTING SEMICONDUCTOR CHIP, AND MODULE IN WHICH SEMICONDUCTOR CHIP IS PACKAGED [patent_app_type] => utility [patent_app_number] => 15/899010 [patent_app_country] => US [patent_app_date] => 2018-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8204 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15899010 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/899010
Semiconductor chip, method for mounting semiconductor chip, and module in which semiconductor chip is packaged Feb 18, 2018 Issued
Array ( [id] => 14191337 [patent_doc_number] => 20190115374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-18 [patent_title] => ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME, DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 16/086278 [patent_app_country] => US [patent_app_date] => 2018-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5662 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16086278 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/086278
Array substrate and method for manufacturing the same, display apparatus Feb 6, 2018 Issued
Array ( [id] => 12888547 [patent_doc_number] => 20180188024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => DETACHABLE PROTECTIVE COVERINGS AND PROTECTION METHODS [patent_app_type] => utility [patent_app_number] => 15/887634 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7476 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887634 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/887634
Detachable protective coverings and protection methods Feb 1, 2018 Issued
Array ( [id] => 13174291 [patent_doc_number] => 10103270 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-16 [patent_title] => Semiconductor device [patent_app_type] => utility [patent_app_number] => 15/881861 [patent_app_country] => US [patent_app_date] => 2018-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 43 [patent_no_of_words] => 22015 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881861 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881861
Semiconductor device Jan 28, 2018 Issued
Array ( [id] => 15889623 [patent_doc_number] => 10651167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-12 [patent_title] => Power FET with a resonant transistor gate [patent_app_type] => utility [patent_app_number] => 15/881164 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10130 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881164 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881164
Power FET with a resonant transistor gate Jan 25, 2018 Issued
Array ( [id] => 13950767 [patent_doc_number] => 10211162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Method for determining misalignment between a first and a second etching zones [patent_app_type] => utility [patent_app_number] => 15/879577 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 20 [patent_no_of_words] => 9774 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 438 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879577 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879577
Method for determining misalignment between a first and a second etching zones Jan 24, 2018 Issued
Array ( [id] => 13320679 [patent_doc_number] => 20180211877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-26 [patent_title] => METHOD OF PROCESSING A WAFER AND WAFER PROCESSING SYSTEM [patent_app_type] => utility [patent_app_number] => 15/879115 [patent_app_country] => US [patent_app_date] => 2018-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10571 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15879115 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/879115
Method of processing a wafer and wafer processing system Jan 23, 2018 Issued
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