Search

Laura Mary Menz

Examiner (ID: 16260)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2273
Issued Applications
1951
Pending Applications
152
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11592777 [patent_doc_number] => 20170117189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'METHOD OF FORMING FIELD EFFECT TRANSISTORS (FETS) WITH ABRUPT JUNCTIONS AND INTEGRATED CIRCUIT CHIPS WITH THE FETS' [patent_app_type] => utility [patent_app_number] => 15/396943 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2882 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396943 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396943
Method of forming field effect transistors (FETs) with abrupt junctions and integrated circuit chips with the FETs Jan 2, 2017 Issued
Array ( [id] => 11592939 [patent_doc_number] => 20170117351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'ACTIVE MATRIX ORGANIC LIGHT-EMITTING-DIODE DISPLAY BACKBOARD AND MANUFACTURING METHOD THEREOF, DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 15/396963 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3746 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396963
Active matrix organic light-emitting-diode display backboard and manufacturing method thereof, display device Jan 2, 2017 Issued
Array ( [id] => 13030807 [patent_doc_number] => 10038027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => CMOS image sensor and fabrication method thereof [patent_app_type] => utility [patent_app_number] => 15/396878 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4436 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396878 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396878
CMOS image sensor and fabrication method thereof Jan 2, 2017 Issued
Array ( [id] => 11939622 [patent_doc_number] => 20170243772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-24 [patent_title] => 'TRANSFER APPARATUS AND METHOD OF MANUFACTURING DISPLAY APPARATUS USING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/396864 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8050 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15396864 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/396864
Transfer apparatus and method of manufacturing display apparatus using the same Jan 2, 2017 Issued
Array ( [id] => 13085073 [patent_doc_number] => 10062609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => Semiconductor devices and methods of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/393506 [patent_app_country] => US [patent_app_date] => 2016-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 5933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15393506 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/393506
Semiconductor devices and methods of manufacturing the same Dec 28, 2016 Issued
Array ( [id] => 14125665 [patent_doc_number] => 10249697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Display panel and display device [patent_app_type] => utility [patent_app_number] => 15/327471 [patent_app_country] => US [patent_app_date] => 2016-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3772 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15327471 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/327471
Display panel and display device Dec 27, 2016 Issued
Array ( [id] => 11571947 [patent_doc_number] => 20170110590 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-20 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/391027 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 21885 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391027 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391027
Semiconductor device and method for manufacturing the same Dec 26, 2016 Issued
Array ( [id] => 14613917 [patent_doc_number] => 10359656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Structure of GOA circuit [patent_app_type] => utility [patent_app_number] => 15/503707 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2331 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15503707 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/503707
Structure of GOA circuit Dec 26, 2016 Issued
Array ( [id] => 11555062 [patent_doc_number] => 20170101308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'Method of Forming a Protective Coating for a Packaged Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 15/388557 [patent_app_country] => US [patent_app_date] => 2016-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4388 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15388557 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/388557
Method of forming a protective coating for a packaged semiconductor device Dec 21, 2016 Issued
Array ( [id] => 11681399 [patent_doc_number] => 09679934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 15/385836 [patent_app_country] => US [patent_app_date] => 2016-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3689 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15385836 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/385836
Semiconductor device Dec 19, 2016 Issued
Array ( [id] => 15139473 [patent_doc_number] => 10483222 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-11-19 [patent_title] => Semiconductor device and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/383923 [patent_app_country] => US [patent_app_date] => 2016-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 6511 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15383923 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/383923
Semiconductor device and manufacturing method thereof Dec 18, 2016 Issued
Array ( [id] => 13211759 [patent_doc_number] => 10120246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-06 [patent_title] => Manufacturing method of IPS array substrate and IPS array substrate [patent_app_type] => utility [patent_app_number] => 15/328495 [patent_app_country] => US [patent_app_date] => 2016-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4101 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15328495 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/328495
Manufacturing method of IPS array substrate and IPS array substrate Dec 14, 2016 Issued
Array ( [id] => 13904283 [patent_doc_number] => 20190041346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-07 [patent_title] => Sensing Layer Formation [patent_app_type] => utility [patent_app_number] => 16/061428 [patent_app_country] => US [patent_app_date] => 2016-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5366 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16061428 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/061428
Sensing layer formation Dec 12, 2016 Issued
Array ( [id] => 11517524 [patent_doc_number] => 20170084598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'INTEGRATED CIRCUIT WITH DUAL STRESS LINER BOUNDARY' [patent_app_type] => utility [patent_app_number] => 15/370651 [patent_app_country] => US [patent_app_date] => 2016-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3192 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15370651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/370651
Integrated circuit with dual stress liner boundary Dec 5, 2016 Issued
Array ( [id] => 13740843 [patent_doc_number] => 20180374891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => METHOD FOR PRODUCING SEMICONDUCTOR EPITAXIAL WAFER AND METHOD OF PRODUCING SOLID-STATE IMAGING DEVICE [patent_app_type] => utility [patent_app_number] => 16/061692 [patent_app_country] => US [patent_app_date] => 2016-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16061692 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/061692
Method for producing semiconductor epitaxial wafer and method of producing solid-state imaging device Dec 4, 2016 Issued
Array ( [id] => 11517760 [patent_doc_number] => 20170084835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'ELECTRODE MATERIALS AND INTERFACE LAYERS TO MINIMIZE CHALCOGENIDE INTERFACE RESISTANCE' [patent_app_type] => utility [patent_app_number] => 15/366364 [patent_app_country] => US [patent_app_date] => 2016-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3998 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15366364 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/366364
Electrode materials and interface layers to minimize chalcogenide interface resistance Nov 30, 2016 Issued
Array ( [id] => 12498480 [patent_doc_number] => 09997454 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => BEOL vertical fuse formed over air gap [patent_app_type] => utility [patent_app_number] => 15/358701 [patent_app_country] => US [patent_app_date] => 2016-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 6315 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15358701 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/358701
BEOL vertical fuse formed over air gap Nov 21, 2016 Issued
Array ( [id] => 11495303 [patent_doc_number] => 20170069488 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-09 [patent_title] => 'METHOD AND SYSTEM FOR THREE-DIMENSIONAL (3D) STRUCTURE FILL' [patent_app_type] => utility [patent_app_number] => 15/356475 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6610 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356475 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356475
Method and system for three-dimensional (3D) structure fill Nov 17, 2016 Issued
Array ( [id] => 14125745 [patent_doc_number] => 10249738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-02 [patent_title] => Nanosheet channel-to-source and drain isolation [patent_app_type] => utility [patent_app_number] => 15/355521 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 36 [patent_no_of_words] => 4802 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15355521 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/355521
Nanosheet channel-to-source and drain isolation Nov 17, 2016 Issued
Array ( [id] => 12734551 [patent_doc_number] => 20180136684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-17 [patent_title] => POWER SYSTEM DISTURBANCE LOCATION DETERMINATION BASED ON RATE OF CHANGE OF FREQUENCY [patent_app_type] => utility [patent_app_number] => 15/353341 [patent_app_country] => US [patent_app_date] => 2016-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15353341 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/353341
Power system disturbance location determination based on rate of change of frequency Nov 15, 2016 Issued
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