Search

Laura Mary Menz

Examiner (ID: 3662)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2142
Issued Applications
1843
Pending Applications
83
Abandoned Applications
195

Applications

Application numberTitle of the applicationFiling DateStatus
08/762304 MULTI-PROCESSING CACHE COHERENCY PROTOCOL ON A LOCAL BUS Dec 8, 1996 Abandoned
Array ( [id] => 4011610 [patent_doc_number] => 05893158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Multibank dram system controlled by multiple dram controllers with an active bank detector' [patent_app_type] => 1 [patent_app_number] => 8/762119 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3942 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893158.pdf [firstpage_image] =>[orig_patent_app_number] => 762119 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/762119
Multibank dram system controlled by multiple dram controllers with an active bank detector Dec 8, 1996 Issued
Array ( [id] => 4018347 [patent_doc_number] => 05924110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Multischeme memory management system for computer' [patent_app_type] => 1 [patent_app_number] => 8/772063 [patent_app_country] => US [patent_app_date] => 1996-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2392 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/924/05924110.pdf [firstpage_image] =>[orig_patent_app_number] => 772063 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/772063
Multischeme memory management system for computer Dec 5, 1996 Issued
Array ( [id] => 3991263 [patent_doc_number] => 05905994 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Magnetic disk controller for backing up cache memory' [patent_app_type] => 1 [patent_app_number] => 8/759459 [patent_app_country] => US [patent_app_date] => 1996-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3378 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905994.pdf [firstpage_image] =>[orig_patent_app_number] => 759459 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/759459
Magnetic disk controller for backing up cache memory Dec 4, 1996 Issued
Array ( [id] => 3892133 [patent_doc_number] => 05805504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Synchronous semiconductor memory having a burst transfer mode with a plurality of subarrays accessible in parallel via an input buffer' [patent_app_type] => 1 [patent_app_number] => 8/758367 [patent_app_country] => US [patent_app_date] => 1996-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9641 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/805/05805504.pdf [firstpage_image] =>[orig_patent_app_number] => 758367 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758367
Synchronous semiconductor memory having a burst transfer mode with a plurality of subarrays accessible in parallel via an input buffer Nov 28, 1996 Issued
Array ( [id] => 4001880 [patent_doc_number] => 05950231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Memory manager system' [patent_app_type] => 1 [patent_app_number] => 8/756200 [patent_app_country] => US [patent_app_date] => 1996-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2188 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/950/05950231.pdf [firstpage_image] =>[orig_patent_app_number] => 756200 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/756200
Memory manager system Nov 24, 1996 Issued
Array ( [id] => 3805669 [patent_doc_number] => 05822759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Cache system' [patent_app_type] => 1 [patent_app_number] => 8/755391 [patent_app_country] => US [patent_app_date] => 1996-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 3924 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822759.pdf [firstpage_image] =>[orig_patent_app_number] => 755391 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/755391
Cache system Nov 21, 1996 Issued
Array ( [id] => 3814241 [patent_doc_number] => 05781922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Page boundary caches' [patent_app_type] => 1 [patent_app_number] => 8/751465 [patent_app_country] => US [patent_app_date] => 1996-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2589 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781922.pdf [firstpage_image] =>[orig_patent_app_number] => 751465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/751465
Page boundary caches Nov 18, 1996 Issued
Array ( [id] => 3888606 [patent_doc_number] => 05893917 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'Memory controller and method of closing a page of system memory' [patent_app_type] => 1 [patent_app_number] => 8/724171 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5136 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893917.pdf [firstpage_image] =>[orig_patent_app_number] => 724171 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724171
Memory controller and method of closing a page of system memory Sep 29, 1996 Issued
Array ( [id] => 4032542 [patent_doc_number] => 05907854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Flash memory file system for writing data files without rewriting an entire volume' [patent_app_type] => 1 [patent_app_number] => 8/721904 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1680 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907854.pdf [firstpage_image] =>[orig_patent_app_number] => 721904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/721904
Flash memory file system for writing data files without rewriting an entire volume Sep 26, 1996 Issued
Array ( [id] => 3897956 [patent_doc_number] => 05765185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'EEPROM array with flash-like core having ECC or a write cache or interruptible load cycles' [patent_app_type] => 1 [patent_app_number] => 8/714605 [patent_app_country] => US [patent_app_date] => 1996-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5750 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765185.pdf [firstpage_image] =>[orig_patent_app_number] => 714605 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714605
EEPROM array with flash-like core having ECC or a write cache or interruptible load cycles Sep 15, 1996 Issued
Array ( [id] => 4020288 [patent_doc_number] => 05860147 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method and apparatus for replacement of entries in a translation look-aside buffer' [patent_app_type] => 1 [patent_app_number] => 8/714894 [patent_app_country] => US [patent_app_date] => 1996-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2370 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860147.pdf [firstpage_image] =>[orig_patent_app_number] => 714894 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/714894
Method and apparatus for replacement of entries in a translation look-aside buffer Sep 15, 1996 Issued
Array ( [id] => 3913440 [patent_doc_number] => 05835954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Target DASD controlled data migration move' [patent_app_type] => 1 [patent_app_number] => 8/711623 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 6116 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835954.pdf [firstpage_image] =>[orig_patent_app_number] => 711623 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711623
Target DASD controlled data migration move Sep 11, 1996 Issued
Array ( [id] => 3741812 [patent_doc_number] => 05671391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Coherent copyback protocol for multi-level cache memory systems' [patent_app_type] => 1 [patent_app_number] => 8/710052 [patent_app_country] => US [patent_app_date] => 1996-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2184 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/671/05671391.pdf [firstpage_image] =>[orig_patent_app_number] => 710052 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710052
Coherent copyback protocol for multi-level cache memory systems Sep 9, 1996 Issued
Array ( [id] => 3853439 [patent_doc_number] => 05761725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Cache-based computer system employing a peripheral bus interface unit with cache write-back suppression and processor-peripheral communication suppression for data coherency' [patent_app_type] => 1 [patent_app_number] => 8/710053 [patent_app_country] => US [patent_app_date] => 1996-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8198 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761725.pdf [firstpage_image] =>[orig_patent_app_number] => 710053 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/710053
Cache-based computer system employing a peripheral bus interface unit with cache write-back suppression and processor-peripheral communication suppression for data coherency Sep 9, 1996 Issued
Array ( [id] => 3812053 [patent_doc_number] => 05781774 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Processor having operating modes for an upgradeable multiprocessor computer system' [patent_app_type] => 1 [patent_app_number] => 8/711318 [patent_app_country] => US [patent_app_date] => 1996-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4511 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781774.pdf [firstpage_image] =>[orig_patent_app_number] => 711318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711318
Processor having operating modes for an upgradeable multiprocessor computer system Sep 2, 1996 Issued
Array ( [id] => 4060975 [patent_doc_number] => 05895491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Apparatus and method for writing an item to a line in a memory table shared by multiple processors' [patent_app_type] => 1 [patent_app_number] => 8/699287 [patent_app_country] => US [patent_app_date] => 1996-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1864 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895491.pdf [firstpage_image] =>[orig_patent_app_number] => 699287 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/699287
Apparatus and method for writing an item to a line in a memory table shared by multiple processors Aug 18, 1996 Issued
Array ( [id] => 4044834 [patent_doc_number] => 05903912 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Microcontroller configured to convey data corresponding to internal memory accesses externally' [patent_app_type] => 1 [patent_app_number] => 8/696733 [patent_app_country] => US [patent_app_date] => 1996-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9346 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903912.pdf [firstpage_image] =>[orig_patent_app_number] => 696733 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/696733
Microcontroller configured to convey data corresponding to internal memory accesses externally Aug 13, 1996 Issued
Array ( [id] => 4020497 [patent_doc_number] => 05860161 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Microcontroller configured to indicate internal memory accesses externally' [patent_app_type] => 1 [patent_app_number] => 8/696735 [patent_app_country] => US [patent_app_date] => 1996-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9303 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860161.pdf [firstpage_image] =>[orig_patent_app_number] => 696735 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/696735
Microcontroller configured to indicate internal memory accesses externally Aug 13, 1996 Issued
Array ( [id] => 4011530 [patent_doc_number] => 05893153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control' [patent_app_type] => 1 [patent_app_number] => 8/691783 [patent_app_country] => US [patent_app_date] => 1996-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5180 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893153.pdf [firstpage_image] =>[orig_patent_app_number] => 691783 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/691783
Method and apparatus for preventing a race condition and maintaining cache coherency in a processor with integrated cache memory and input/output control Aug 1, 1996 Issued
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