Search

Laura Mary Menz

Examiner (ID: 16260)

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2273
Issued Applications
1951
Pending Applications
152
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10733242 [patent_doc_number] => 20160079392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'Drain Extended CMOS with Counter-Doped Drain Extension' [patent_app_type] => utility [patent_app_number] => 14/949241 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4089 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14949241 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/949241
Drain extended CMOS with counter-doped drain extension Nov 22, 2015 Issued
Array ( [id] => 11180621 [patent_doc_number] => 09412616 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-08-09 [patent_title] => 'Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products' [patent_app_type] => utility [patent_app_number] => 14/942448 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 28 [patent_no_of_words] => 7921 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942448 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942448
Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products Nov 15, 2015 Issued
Array ( [id] => 11918423 [patent_doc_number] => 09786614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-10 [patent_title] => 'Integrated fan-out structure and method of forming' [patent_app_type] => utility [patent_app_number] => 14/942627 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 22 [patent_no_of_words] => 6422 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942627 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942627
Integrated fan-out structure and method of forming Nov 15, 2015 Issued
Array ( [id] => 11862141 [patent_doc_number] => 09741835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Semiconductor device and insulated gate bipolar transistor with transistor cells and sensor cell' [patent_app_type] => utility [patent_app_number] => 14/942623 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942623 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942623
Semiconductor device and insulated gate bipolar transistor with transistor cells and sensor cell Nov 15, 2015 Issued
Array ( [id] => 11862141 [patent_doc_number] => 09741835 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-22 [patent_title] => 'Semiconductor device and insulated gate bipolar transistor with transistor cells and sensor cell' [patent_app_type] => utility [patent_app_number] => 14/942623 [patent_app_country] => US [patent_app_date] => 2015-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4517 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14942623 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/942623
Semiconductor device and insulated gate bipolar transistor with transistor cells and sensor cell Nov 15, 2015 Issued
Array ( [id] => 11483575 [patent_doc_number] => 09590137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Light-emitting diode' [patent_app_type] => utility [patent_app_number] => 14/940123 [patent_app_country] => US [patent_app_date] => 2015-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 73 [patent_no_of_words] => 29402 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14940123 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/940123
Light-emitting diode Nov 11, 2015 Issued
Array ( [id] => 12953560 [patent_doc_number] => 09837331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-12-05 [patent_title] => Semiconductor device having overlapped via apertures [patent_app_type] => utility [patent_app_number] => 14/924994 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14924994 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/924994
Semiconductor device having overlapped via apertures Oct 27, 2015 Issued
Array ( [id] => 10689560 [patent_doc_number] => 20160035707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'STACKED STRUCTURE OF SEMICONDUCTOR CHIPS HAVING VIA HOLES AND METAL BUMPS' [patent_app_type] => utility [patent_app_number] => 14/883135 [patent_app_country] => US [patent_app_date] => 2015-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 10980 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14883135 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/883135
Stacked structure of semiconductor chips having via holes and metal bumps Oct 13, 2015 Issued
Array ( [id] => 10689561 [patent_doc_number] => 20160035706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'SEMICONDUCTOR DEVICE FOR BATTERY POWER VOLTAGE CONTROL' [patent_app_type] => utility [patent_app_number] => 14/881481 [patent_app_country] => US [patent_app_date] => 2015-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 19580 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14881481 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/881481
SEMICONDUCTOR DEVICE FOR BATTERY POWER VOLTAGE CONTROL Oct 12, 2015 Abandoned
Array ( [id] => 10826283 [patent_doc_number] => 20160172451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-16 [patent_title] => 'SEMICONDUCTOR ARRANGEMENT' [patent_app_type] => utility [patent_app_number] => 14/879394 [patent_app_country] => US [patent_app_date] => 2015-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3768 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14879394 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/879394
Semiconductor arrangement Oct 8, 2015 Issued
Array ( [id] => 10689447 [patent_doc_number] => 20160035594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-04 [patent_title] => 'ELECTRONIC COMPONENT WITH A LEADFRAME' [patent_app_type] => utility [patent_app_number] => 14/880072 [patent_app_country] => US [patent_app_date] => 2015-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1679 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14880072 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/880072
Electronic component with a leadframe Oct 8, 2015 Issued
14/875562 PRODUCT AND PROCESS FOR ENABLING A CLOG-RESISTANT FEATURE IN A HAND-HELD LEAF RAKE Oct 4, 2015 Abandoned
Array ( [id] => 10745247 [patent_doc_number] => 20160091398 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'METHODS FOR USING DIGITIZED SOUND PATTERNS TO MONITOR OPERATION OF AUTOMATED MACHINERY' [patent_app_type] => utility [patent_app_number] => 14/870256 [patent_app_country] => US [patent_app_date] => 2015-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14870256 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/870256
Methods for using digitized sound patterns to monitor operation of automated machinery Sep 29, 2015 Issued
Array ( [id] => 11028803 [patent_doc_number] => 20160225759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-04 [patent_title] => 'POWER FET WITH A RESONANT TRANSISTOR GATE' [patent_app_type] => utility [patent_app_number] => 14/868700 [patent_app_country] => US [patent_app_date] => 2015-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10670 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868700 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/868700
Power FET with a resonant transistor gate Sep 28, 2015 Issued
Array ( [id] => 11539577 [patent_doc_number] => 09613995 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-04 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 14/864912 [patent_app_country] => US [patent_app_date] => 2015-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3897 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/864912
Method of manufacturing semiconductor device Sep 24, 2015 Issued
Array ( [id] => 11453396 [patent_doc_number] => 09577048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-02-21 [patent_title] => 'Heterostructure field-effect transistor' [patent_app_type] => utility [patent_app_number] => 14/864680 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 4414 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864680 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/864680
Heterostructure field-effect transistor Sep 23, 2015 Issued
Array ( [id] => 10611189 [patent_doc_number] => 09331235 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/863687 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 26 [patent_no_of_words] => 10371 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14863687 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/863687
Semiconductor device and method for manufacturing the same Sep 23, 2015 Issued
Array ( [id] => 13043377 [patent_doc_number] => 10043830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-07 [patent_title] => Thin film transistor circuit device and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 14/864451 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 5786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864451 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/864451
Thin film transistor circuit device and method of manufacturing the same Sep 23, 2015 Issued
Array ( [id] => 11575586 [patent_doc_number] => 09630833 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Method to improve cantilever process performance' [patent_app_type] => utility [patent_app_number] => 14/864851 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4117 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14864851 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/864851
Method to improve cantilever process performance Sep 23, 2015 Issued
Array ( [id] => 10667169 [patent_doc_number] => 20160013314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-14 [patent_title] => 'INTEGRATED CIRCUIT WITH DUAL STRESS LINER BOUNDARY' [patent_app_type] => utility [patent_app_number] => 14/863249 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3168 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14863249 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/863249
Integrated circuit with dual stress liner boundary Sep 22, 2015 Issued
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