Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8270817 [patent_doc_number] => 08212316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same' [patent_app_type] => utility [patent_app_number] => 12/549923 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 21256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12549923 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549923
Integrated circuit with a laterally diffused metal oxide semiconductor device and method of forming the same Aug 27, 2009 Issued
Array ( [id] => 7656901 [patent_doc_number] => 20110306170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process' [patent_app_type] => utility [patent_app_number] => 12/549908 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2280 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0306/20110306170.pdf [firstpage_image] =>[orig_patent_app_number] => 12549908 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549908
Novel Method to Improve Performance by Enhancing Poly Gate Doping Concentration in an Embedded SiGe PMOS Process Aug 27, 2009 Abandoned
Array ( [id] => 6501690 [patent_doc_number] => 20100012956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-21 [patent_title] => 'Diode having high brightness and method thereof' [patent_app_type] => utility [patent_app_number] => 12/461681 [patent_app_country] => US [patent_app_date] => 2009-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4146 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0012/20100012956.pdf [firstpage_image] =>[orig_patent_app_number] => 12461681 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/461681
Diode having high brightness and method thereof Aug 19, 2009 Issued
Array ( [id] => 8340592 [patent_doc_number] => 08242516 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Organic EL display panel and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 12/679322 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 9908 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12679322 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/679322
Organic EL display panel and method of manufacturing the same Aug 16, 2009 Issued
Array ( [id] => 6489952 [patent_doc_number] => 20100009526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'FABRICATION METHOD AND FABRICATION APPARATUS OF GROUP III NITRIDE CRYSTAL SUBSTANCE' [patent_app_type] => utility [patent_app_number] => 12/540492 [patent_app_country] => US [patent_app_date] => 2009-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 15167 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20100009526.pdf [firstpage_image] =>[orig_patent_app_number] => 12540492 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/540492
Fabrication method and fabrication apparatus of group III nitride crystal substance Aug 12, 2009 Issued
Array ( [id] => 8146640 [patent_doc_number] => 08163642 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-24 [patent_title] => 'Package substrate with dual material build-up layers' [patent_app_type] => utility [patent_app_number] => 12/540262 [patent_app_country] => US [patent_app_date] => 2009-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2991 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/163/08163642.pdf [firstpage_image] =>[orig_patent_app_number] => 12540262 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/540262
Package substrate with dual material build-up layers Aug 11, 2009 Issued
Array ( [id] => 4538190 [patent_doc_number] => 07888774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Interconnect line selectively isolated from an underlying contact plug' [patent_app_type] => utility [patent_app_number] => 12/503685 [patent_app_country] => US [patent_app_date] => 2009-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3462 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888774.pdf [firstpage_image] =>[orig_patent_app_number] => 12503685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/503685
Interconnect line selectively isolated from an underlying contact plug Jul 14, 2009 Issued
Array ( [id] => 5558294 [patent_doc_number] => 20090269871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-29 [patent_title] => 'EL Display Device and Method of Manufacturing the Same' [patent_app_type] => utility [patent_app_number] => 12/500862 [patent_app_country] => US [patent_app_date] => 2009-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 20209 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0269/20090269871.pdf [firstpage_image] =>[orig_patent_app_number] => 12500862 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/500862
EL display device and method of manufacturing the same Jul 9, 2009 Issued
Array ( [id] => 8435493 [patent_doc_number] => 08283262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-09 [patent_title] => 'Method for depositing a layer on a semiconductor wafer by means of CVD and chamber for carrying out the method' [patent_app_type] => utility [patent_app_number] => 12/499924 [patent_app_country] => US [patent_app_date] => 2009-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2515 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12499924 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/499924
Method for depositing a layer on a semiconductor wafer by means of CVD and chamber for carrying out the method Jul 8, 2009 Issued
Array ( [id] => 7987847 [patent_doc_number] => 08076218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Method for the production of photo-patterned carbon electronics' [patent_app_type] => utility [patent_app_number] => 12/497752 [patent_app_country] => US [patent_app_date] => 2009-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3374 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/076/08076218.pdf [firstpage_image] =>[orig_patent_app_number] => 12497752 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/497752
Method for the production of photo-patterned carbon electronics Jul 5, 2009 Issued
Array ( [id] => 5364763 [patent_doc_number] => 20090302322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'Method of Forming a Thin Film Transistor' [patent_app_type] => utility [patent_app_number] => 12/492991 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3386 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20090302322.pdf [firstpage_image] =>[orig_patent_app_number] => 12492991 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492991
Method of Forming a Thin Film Transistor Jun 25, 2009 Abandoned
Array ( [id] => 7555378 [patent_doc_number] => 08067279 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-29 [patent_title] => 'Application of different isolation schemes for logic and embedded memory' [patent_app_type] => utility [patent_app_number] => 12/489223 [patent_app_country] => US [patent_app_date] => 2009-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 32 [patent_no_of_words] => 8551 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/067/08067279.pdf [firstpage_image] =>[orig_patent_app_number] => 12489223 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/489223
Application of different isolation schemes for logic and embedded memory Jun 21, 2009 Issued
Array ( [id] => 8410256 [patent_doc_number] => 08273653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Microscopic structure packaging method and device with packaged microscopic structure' [patent_app_type] => utility [patent_app_number] => 12/477798 [patent_app_country] => US [patent_app_date] => 2009-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2653 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12477798 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/477798
Microscopic structure packaging method and device with packaged microscopic structure Jun 2, 2009 Issued
Array ( [id] => 6026722 [patent_doc_number] => 20110079767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'NITRIDE SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/995773 [patent_app_country] => US [patent_app_date] => 2009-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7568 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079767.pdf [firstpage_image] =>[orig_patent_app_number] => 12995773 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/995773
NITRIDE SEMICONDUCTOR DEVICE Jun 2, 2009 Abandoned
Array ( [id] => 5530772 [patent_doc_number] => 20090230560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/453715 [patent_app_country] => US [patent_app_date] => 2009-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 8385 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20090230560.pdf [firstpage_image] =>[orig_patent_app_number] => 12453715 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453715
Semiconductor device and manufacturing method thereof May 19, 2009 Issued
Array ( [id] => 6120837 [patent_doc_number] => 20110084356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'LOCAL BURIED LAYER FORMING METHOD AND SEMICONDUCTOR DEVICE HAVING SUCH A LAYER' [patent_app_type] => utility [patent_app_number] => 12/995764 [patent_app_country] => US [patent_app_date] => 2009-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4906 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20110084356.pdf [firstpage_image] =>[orig_patent_app_number] => 12995764 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/995764
LOCAL BURIED LAYER FORMING METHOD AND SEMICONDUCTOR DEVICE HAVING SUCH A LAYER May 19, 2009 Abandoned
Array ( [id] => 4537492 [patent_doc_number] => 07888677 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films' [patent_app_type] => utility [patent_app_number] => 12/467967 [patent_app_country] => US [patent_app_date] => 2009-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 42 [patent_no_of_words] => 10058 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888677.pdf [firstpage_image] =>[orig_patent_app_number] => 12467967 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467967
Method for manufacturing a thin film transistor array panel for a liquid crystal display and a photolithography method for fabricating thin films May 17, 2009 Issued
Array ( [id] => 5383162 [patent_doc_number] => 20090224406 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'Dense Seed Layer and Method of Formation' [patent_app_type] => utility [patent_app_number] => 12/467065 [patent_app_country] => US [patent_app_date] => 2009-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6391 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20090224406.pdf [firstpage_image] =>[orig_patent_app_number] => 12467065 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/467065
Dense seed layer and method of formation May 14, 2009 Issued
Array ( [id] => 5315979 [patent_doc_number] => 20090280577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-12 [patent_title] => 'Manufacturing method of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/453451 [patent_app_country] => US [patent_app_date] => 2009-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 18487 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20090280577.pdf [firstpage_image] =>[orig_patent_app_number] => 12453451 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/453451
Manufacturing method of a semiconductor device May 11, 2009 Issued
Array ( [id] => 81638 [patent_doc_number] => 07745343 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-29 [patent_title] => 'Method for fabricating semiconductor device with fuse element' [patent_app_type] => utility [patent_app_number] => 12/431643 [patent_app_country] => US [patent_app_date] => 2009-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2407 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/745/07745343.pdf [firstpage_image] =>[orig_patent_app_number] => 12431643 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/431643
Method for fabricating semiconductor device with fuse element Apr 27, 2009 Issued
Menu