Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 102490 [patent_doc_number] => 07723231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/889576 [patent_app_country] => US [patent_app_date] => 2007-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4873 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/723/07723231.pdf [firstpage_image] =>[orig_patent_app_number] => 11889576 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/889576
Semiconductor device and method of fabricating the same Aug 13, 2007 Issued
Array ( [id] => 4442092 [patent_doc_number] => 07928019 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-19 [patent_title] => 'Semiconductor processing' [patent_app_type] => utility [patent_app_number] => 11/891575 [patent_app_country] => US [patent_app_date] => 2007-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 11676 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/928/07928019.pdf [firstpage_image] =>[orig_patent_app_number] => 11891575 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/891575
Semiconductor processing Aug 9, 2007 Issued
Array ( [id] => 4639394 [patent_doc_number] => 08017421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Method of manufacturing semiconductor light emitting device' [patent_app_type] => utility [patent_app_number] => 11/889126 [patent_app_country] => US [patent_app_date] => 2007-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 3442 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/017/08017421.pdf [firstpage_image] =>[orig_patent_app_number] => 11889126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/889126
Method of manufacturing semiconductor light emitting device Aug 8, 2007 Issued
Array ( [id] => 83534 [patent_doc_number] => 07741206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Pad structure for liquid crystal display and method of manufacturing thereof' [patent_app_type] => utility [patent_app_number] => 11/889184 [patent_app_country] => US [patent_app_date] => 2007-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 5277 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/741/07741206.pdf [firstpage_image] =>[orig_patent_app_number] => 11889184 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/889184
Pad structure for liquid crystal display and method of manufacturing thereof Aug 8, 2007 Issued
Array ( [id] => 4488657 [patent_doc_number] => 07884360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Thin-film device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/890426 [patent_app_country] => US [patent_app_date] => 2007-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 29 [patent_no_of_words] => 10853 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/884/07884360.pdf [firstpage_image] =>[orig_patent_app_number] => 11890426 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/890426
Thin-film device and method of fabricating the same Aug 5, 2007 Issued
Array ( [id] => 173748 [patent_doc_number] => 07659127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Manufacturing device of semiconductor package and manufacturing method of semiconductor package' [patent_app_type] => utility [patent_app_number] => 11/882136 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 12655 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/659/07659127.pdf [firstpage_image] =>[orig_patent_app_number] => 11882136 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/882136
Manufacturing device of semiconductor package and manufacturing method of semiconductor package Jul 30, 2007 Issued
Array ( [id] => 5361105 [patent_doc_number] => 20090035899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-05 [patent_title] => 'Microelectronic device' [patent_app_type] => utility [patent_app_number] => 11/888055 [patent_app_country] => US [patent_app_date] => 2007-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1941 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20090035899.pdf [firstpage_image] =>[orig_patent_app_number] => 11888055 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/888055
Microelectronic device Jul 30, 2007 Issued
Array ( [id] => 4608874 [patent_doc_number] => 07994021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/881285 [patent_app_country] => US [patent_app_date] => 2007-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 87 [patent_no_of_words] => 21772 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/994/07994021.pdf [firstpage_image] =>[orig_patent_app_number] => 11881285 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/881285
Method of manufacturing semiconductor device Jul 24, 2007 Issued
Array ( [id] => 311025 [patent_doc_number] => 07528049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-05 [patent_title] => 'Method for manufacturing bonded SOI wafer and bonded SOI wafer manufactured thereby' [patent_app_type] => utility [patent_app_number] => 11/878255 [patent_app_country] => US [patent_app_date] => 2007-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5128 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/528/07528049.pdf [firstpage_image] =>[orig_patent_app_number] => 11878255 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/878255
Method for manufacturing bonded SOI wafer and bonded SOI wafer manufactured thereby Jul 22, 2007 Issued
Array ( [id] => 4457504 [patent_doc_number] => 07893424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-22 [patent_title] => 'Semiconductor layer structure with superlattice' [patent_app_type] => utility [patent_app_number] => 11/780514 [patent_app_country] => US [patent_app_date] => 2007-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5648 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/893/07893424.pdf [firstpage_image] =>[orig_patent_app_number] => 11780514 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/780514
Semiconductor layer structure with superlattice Jul 19, 2007 Issued
Array ( [id] => 5046107 [patent_doc_number] => 20070264780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-15 [patent_title] => 'Method of fabricating a vertical nano-transistor' [patent_app_type] => utility [patent_app_number] => 11/879435 [patent_app_country] => US [patent_app_date] => 2007-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1267 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20070264780.pdf [firstpage_image] =>[orig_patent_app_number] => 11879435 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/879435
Method of fabricating a vertical nano-transistor Jul 16, 2007 Abandoned
Array ( [id] => 4752656 [patent_doc_number] => 20080160731 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'METHOD FOR FABRICATING CMOS IMAGE SENSOR' [patent_app_type] => utility [patent_app_number] => 11/778475 [patent_app_country] => US [patent_app_date] => 2007-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2827 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20080160731.pdf [firstpage_image] =>[orig_patent_app_number] => 11778475 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/778475
METHOD FOR FABRICATING CMOS IMAGE SENSOR Jul 15, 2007 Abandoned
Array ( [id] => 314791 [patent_doc_number] => 07524761 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-04-28 [patent_title] => 'Method for manufacturing semiconductor device capable of reducing parasitic bit line capacitance' [patent_app_type] => utility [patent_app_number] => 11/776905 [patent_app_country] => US [patent_app_date] => 2007-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2691 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/524/07524761.pdf [firstpage_image] =>[orig_patent_app_number] => 11776905 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/776905
Method for manufacturing semiconductor device capable of reducing parasitic bit line capacitance Jul 11, 2007 Issued
Array ( [id] => 43567 [patent_doc_number] => 07776661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Nano-electromechanical circuit using co-planar transmission line' [patent_app_type] => utility [patent_app_number] => 11/776254 [patent_app_country] => US [patent_app_date] => 2007-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4107 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/776/07776661.pdf [firstpage_image] =>[orig_patent_app_number] => 11776254 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/776254
Nano-electromechanical circuit using co-planar transmission line Jul 10, 2007 Issued
Array ( [id] => 141644 [patent_doc_number] => 07687309 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-30 [patent_title] => 'CMOS-process-compatible programmable via device' [patent_app_type] => utility [patent_app_number] => 11/770455 [patent_app_country] => US [patent_app_date] => 2007-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 4104 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/687/07687309.pdf [firstpage_image] =>[orig_patent_app_number] => 11770455 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/770455
CMOS-process-compatible programmable via device Jun 27, 2007 Issued
Array ( [id] => 4613001 [patent_doc_number] => 07989350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Method for fabricating semiconductor device with recess gate' [patent_app_type] => utility [patent_app_number] => 11/769465 [patent_app_country] => US [patent_app_date] => 2007-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 2787 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/989/07989350.pdf [firstpage_image] =>[orig_patent_app_number] => 11769465 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/769465
Method for fabricating semiconductor device with recess gate Jun 26, 2007 Issued
Array ( [id] => 5210499 [patent_doc_number] => 20070249083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-25 [patent_title] => 'Multilevel phase-change memory element and operating method' [patent_app_type] => utility [patent_app_number] => 11/819063 [patent_app_country] => US [patent_app_date] => 2007-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5222 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0249/20070249083.pdf [firstpage_image] =>[orig_patent_app_number] => 11819063 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/819063
Multilevel phase-change memory element and operating method Jun 24, 2007 Abandoned
Array ( [id] => 602352 [patent_doc_number] => 07432115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-07 [patent_title] => 'Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit' [patent_app_type] => utility [patent_app_number] => 11/808861 [patent_app_country] => US [patent_app_date] => 2007-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 10428 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/432/07432115.pdf [firstpage_image] =>[orig_patent_app_number] => 11808861 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/808861
Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit Jun 12, 2007 Issued
Array ( [id] => 4955037 [patent_doc_number] => 20080188061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-08-07 [patent_title] => 'METHOD OF PROTECTING FRONT SURFACE STRUCTURE OF WAFER AND METHOD OF WAFER DIVIDING' [patent_app_type] => utility [patent_app_number] => 11/762036 [patent_app_country] => US [patent_app_date] => 2007-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1748 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20080188061.pdf [firstpage_image] =>[orig_patent_app_number] => 11762036 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/762036
METHOD OF PROTECTING FRONT SURFACE STRUCTURE OF WAFER AND METHOD OF WAFER DIVIDING Jun 11, 2007 Abandoned
Array ( [id] => 5247438 [patent_doc_number] => 20070243672 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-18 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/808164 [patent_app_country] => US [patent_app_date] => 2007-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 7628 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20070243672.pdf [firstpage_image] =>[orig_patent_app_number] => 11808164 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/808164
Semiconductor device and method for fabricating the same Jun 6, 2007 Abandoned
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