Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5214553 [patent_doc_number] => 20070103633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-10 [patent_title] => 'Liquid crystal display device having more uniform seal heights and its fabricating method' [patent_app_type] => utility [patent_app_number] => 11/646531 [patent_app_country] => US [patent_app_date] => 2006-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4222 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0103/20070103633.pdf [firstpage_image] =>[orig_patent_app_number] => 11646531 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646531
Liquid crystal display device having more uniform seal heights and its fabricating method Dec 27, 2006 Issued
Array ( [id] => 169644 [patent_doc_number] => 07667291 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-23 [patent_title] => 'FPGA structure provided with multi parallel structure and method for forming the same' [patent_app_type] => utility [patent_app_number] => 11/645656 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5213 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/667/07667291.pdf [firstpage_image] =>[orig_patent_app_number] => 11645656 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/645656
FPGA structure provided with multi parallel structure and method for forming the same Dec 26, 2006 Issued
Array ( [id] => 4704680 [patent_doc_number] => 20080064204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Method of forming a metal line of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/646925 [patent_app_country] => US [patent_app_date] => 2006-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2051 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20080064204.pdf [firstpage_image] =>[orig_patent_app_number] => 11646925 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/646925
Method of forming a metal line of a semiconductor device Dec 26, 2006 Issued
Array ( [id] => 191347 [patent_doc_number] => 07642660 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Method and apparatus for reducing electrical interconnection fatigue' [patent_app_type] => utility [patent_app_number] => 11/616164 [patent_app_country] => US [patent_app_date] => 2006-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2654 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642660.pdf [firstpage_image] =>[orig_patent_app_number] => 11616164 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/616164
Method and apparatus for reducing electrical interconnection fatigue Dec 25, 2006 Issued
Array ( [id] => 243266 [patent_doc_number] => 07589000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Fabrication method and fabrication apparatus of group III nitride crystal substance' [patent_app_type] => utility [patent_app_number] => 11/643675 [patent_app_country] => US [patent_app_date] => 2006-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 15168 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/589/07589000.pdf [firstpage_image] =>[orig_patent_app_number] => 11643675 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/643675
Fabrication method and fabrication apparatus of group III nitride crystal substance Dec 21, 2006 Issued
Array ( [id] => 578902 [patent_doc_number] => 07452760 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-18 [patent_title] => 'Thin film transistors and semiconductor constructions' [patent_app_type] => utility [patent_app_number] => 11/644863 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3341 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/452/07452760.pdf [firstpage_image] =>[orig_patent_app_number] => 11644863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/644863
Thin film transistors and semiconductor constructions Dec 20, 2006 Issued
Array ( [id] => 5022941 [patent_doc_number] => 20070148907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-28 [patent_title] => 'Method of forming isolation layer of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/642546 [patent_app_country] => US [patent_app_date] => 2006-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1730 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20070148907.pdf [firstpage_image] =>[orig_patent_app_number] => 11642546 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/642546
Method of forming isolation layer of semiconductor device Dec 20, 2006 Issued
Array ( [id] => 4863883 [patent_doc_number] => 20080142942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-19 [patent_title] => 'METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING' [patent_app_type] => utility [patent_app_number] => 11/612992 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0142/20080142942.pdf [firstpage_image] =>[orig_patent_app_number] => 11612992 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612992
Method and apparatus for multi-chip packaging Dec 18, 2006 Issued
Array ( [id] => 5219900 [patent_doc_number] => 20070161211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-12 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/641336 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 3659 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20070161211.pdf [firstpage_image] =>[orig_patent_app_number] => 11641336 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/641336
Method for manufacturing semiconductor device Dec 18, 2006 Issued
Array ( [id] => 586968 [patent_doc_number] => 07439130 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Semiconductor device with capacitor and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/612606 [patent_app_country] => US [patent_app_date] => 2006-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3651 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/439/07439130.pdf [firstpage_image] =>[orig_patent_app_number] => 11612606 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/612606
Semiconductor device with capacitor and method for fabricating the same Dec 18, 2006 Issued
Array ( [id] => 202556 [patent_doc_number] => 07632746 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-12-15 [patent_title] => 'Method for patterning metal line in semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/641295 [patent_app_country] => US [patent_app_date] => 2006-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1720 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/632/07632746.pdf [firstpage_image] =>[orig_patent_app_number] => 11641295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/641295
Method for patterning metal line in semiconductor device Dec 17, 2006 Issued
Array ( [id] => 260360 [patent_doc_number] => 07573087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-08-11 [patent_title] => 'Interconnect line selectively isolated from an underlying contact plug' [patent_app_type] => utility [patent_app_number] => 11/639218 [patent_app_country] => US [patent_app_date] => 2006-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 3436 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/573/07573087.pdf [firstpage_image] =>[orig_patent_app_number] => 11639218 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/639218
Interconnect line selectively isolated from an underlying contact plug Dec 14, 2006 Issued
Array ( [id] => 584814 [patent_doc_number] => 07442580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'Manufacturing method of a package structure' [patent_app_type] => utility [patent_app_number] => 11/637786 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 1918 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/442/07442580.pdf [firstpage_image] =>[orig_patent_app_number] => 11637786 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/637786
Manufacturing method of a package structure Dec 12, 2006 Issued
Array ( [id] => 4444668 [patent_doc_number] => 07863171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-04 [patent_title] => 'SOI transistor having a reduced body potential and a method of forming the same' [patent_app_type] => utility [patent_app_number] => 11/609995 [patent_app_country] => US [patent_app_date] => 2006-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 7772 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/863/07863171.pdf [firstpage_image] =>[orig_patent_app_number] => 11609995 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/609995
SOI transistor having a reduced body potential and a method of forming the same Dec 12, 2006 Issued
Array ( [id] => 5116823 [patent_doc_number] => 20070138537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING A NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 11/609885 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 1822 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138537.pdf [firstpage_image] =>[orig_patent_app_number] => 11609885 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/609885
NON-VOLATILE MEMORY DEVICE AND METHOD OF FABRICATING A NON-VOLATILE MEMORY DEVICE Dec 11, 2006 Abandoned
Array ( [id] => 5250580 [patent_doc_number] => 20070132036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/637056 [patent_app_country] => US [patent_app_date] => 2006-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1683 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0132/20070132036.pdf [firstpage_image] =>[orig_patent_app_number] => 11637056 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/637056
Method of manufacturing semiconductor device Dec 11, 2006 Issued
Array ( [id] => 4569195 [patent_doc_number] => 07847214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Laser crystallization apparatus and crystallization method' [patent_app_type] => utility [patent_app_number] => 11/567383 [patent_app_country] => US [patent_app_date] => 2006-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 12367 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/847/07847214.pdf [firstpage_image] =>[orig_patent_app_number] => 11567383 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/567383
Laser crystallization apparatus and crystallization method Dec 5, 2006 Issued
Array ( [id] => 5174808 [patent_doc_number] => 20070175865 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-02 [patent_title] => 'PROCESS FOR THE FABRICATION OF AN INERTIAL SENSOR WITH FAILURE THRESHOLD' [patent_app_type] => utility [patent_app_number] => 11/566590 [patent_app_country] => US [patent_app_date] => 2006-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5112 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20070175865.pdf [firstpage_image] =>[orig_patent_app_number] => 11566590 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/566590
Process for the fabrication of an inertial sensor with failure threshold Dec 3, 2006 Issued
Array ( [id] => 142681 [patent_doc_number] => 07687887 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-03-30 [patent_title] => 'Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter' [patent_app_type] => utility [patent_app_number] => 11/607265 [patent_app_country] => US [patent_app_date] => 2006-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 43 [patent_no_of_words] => 4295 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/687/07687887.pdf [firstpage_image] =>[orig_patent_app_number] => 11607265 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/607265
Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter Nov 30, 2006 Issued
Array ( [id] => 121526 [patent_doc_number] => 07709356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-04 [patent_title] => 'Methods of forming a pattern and methods of manufacturing a memory device using the same' [patent_app_type] => utility [patent_app_number] => 11/605266 [patent_app_country] => US [patent_app_date] => 2006-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 7310 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/709/07709356.pdf [firstpage_image] =>[orig_patent_app_number] => 11605266 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/605266
Methods of forming a pattern and methods of manufacturing a memory device using the same Nov 28, 2006 Issued
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