
Laura Mary Menz
Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813 |
| Total Applications | 2324 |
| Issued Applications | 1995 |
| Pending Applications | 138 |
| Abandoned Applications | 216 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5214553
[patent_doc_number] => 20070103633
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-05-10
[patent_title] => 'Liquid crystal display device having more uniform seal heights and its fabricating method'
[patent_app_type] => utility
[patent_app_number] => 11/646531
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/646531 | Liquid crystal display device having more uniform seal heights and its fabricating method | Dec 27, 2006 | Issued |
Array
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[patent_doc_number] => 07667291
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-02-23
[patent_title] => 'FPGA structure provided with multi parallel structure and method for forming the same'
[patent_app_type] => utility
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[patent_app_date] => 2006-12-27
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/645656 | FPGA structure provided with multi parallel structure and method for forming the same | Dec 26, 2006 | Issued |
Array
(
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[patent_issue_date] => 2008-03-13
[patent_title] => 'Method of forming a metal line of a semiconductor device'
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Array
(
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[patent_kind] => B2
[patent_issue_date] => 2010-01-05
[patent_title] => 'Method and apparatus for reducing electrical interconnection fatigue'
[patent_app_type] => utility
[patent_app_number] => 11/616164
[patent_app_country] => US
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Array
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[patent_title] => 'Fabrication method and fabrication apparatus of group III nitride crystal substance'
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Array
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[patent_title] => 'Thin film transistors and semiconductor constructions'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/644863 | Thin film transistors and semiconductor constructions | Dec 20, 2006 | Issued |
Array
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[id] => 5022941
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[patent_title] => 'Method of forming isolation layer of semiconductor device'
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/642546 | Method of forming isolation layer of semiconductor device | Dec 20, 2006 | Issued |
Array
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[id] => 4863883
[patent_doc_number] => 20080142942
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[patent_kind] => A1
[patent_issue_date] => 2008-06-19
[patent_title] => 'METHOD AND APPARATUS FOR MULTI-CHIP PACKAGING'
[patent_app_type] => utility
[patent_app_number] => 11/612992
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/612992 | Method and apparatus for multi-chip packaging | Dec 18, 2006 | Issued |
Array
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Array
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[patent_title] => 'Semiconductor device with capacitor and method for fabricating the same'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/641295 | Method for patterning metal line in semiconductor device | Dec 17, 2006 | Issued |
Array
(
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[patent_title] => 'Interconnect line selectively isolated from an underlying contact plug'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/639218 | Interconnect line selectively isolated from an underlying contact plug | Dec 14, 2006 | Issued |
Array
(
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Array
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Array
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