Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5912979 [patent_doc_number] => 20060128041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Misalignment test structure and method thereof' [patent_app_type] => utility [patent_app_number] => 11/339687 [patent_app_country] => US [patent_app_date] => 2006-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3826 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20060128041.pdf [firstpage_image] =>[orig_patent_app_number] => 11339687 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/339687
Misalignment test structure and method thereof Jan 25, 2006 Issued
Array ( [id] => 568546 [patent_doc_number] => 07462564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Processing system and method for treating a substrate' [patent_app_type] => utility [patent_app_number] => 11/337654 [patent_app_country] => US [patent_app_date] => 2006-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 9168 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/462/07462564.pdf [firstpage_image] =>[orig_patent_app_number] => 11337654 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/337654
Processing system and method for treating a substrate Jan 23, 2006 Issued
Array ( [id] => 71447 [patent_doc_number] => 07754508 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-13 [patent_title] => 'Method of manufacturing silicon optoelectronic device, silicon optoelectronic device manufactured by the method, and image input and/or output apparatus using the silicon optoelectronic device' [patent_app_type] => utility [patent_app_number] => 11/335503 [patent_app_country] => US [patent_app_date] => 2006-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 29 [patent_no_of_words] => 8966 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/754/07754508.pdf [firstpage_image] =>[orig_patent_app_number] => 11335503 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/335503
Method of manufacturing silicon optoelectronic device, silicon optoelectronic device manufactured by the method, and image input and/or output apparatus using the silicon optoelectronic device Jan 19, 2006 Issued
Array ( [id] => 348824 [patent_doc_number] => 07494940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-24 [patent_title] => 'Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 11/333741 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 7159 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/494/07494940.pdf [firstpage_image] =>[orig_patent_app_number] => 11333741 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/333741
Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices Jan 16, 2006 Issued
Array ( [id] => 5843610 [patent_doc_number] => 20060121695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Method for manufacturing semiconductor thin film' [patent_app_type] => utility [patent_app_number] => 11/330213 [patent_app_country] => US [patent_app_date] => 2006-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 22594 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20060121695.pdf [firstpage_image] =>[orig_patent_app_number] => 11330213 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/330213
Method for manufacturing semiconductor thin film Jan 11, 2006 Issued
Array ( [id] => 5596451 [patent_doc_number] => 20060160368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-20 [patent_title] => 'Substrate processing apparatus and substrate processing method' [patent_app_type] => utility [patent_app_number] => 11/327310 [patent_app_country] => US [patent_app_date] => 2006-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10105 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0160/20060160368.pdf [firstpage_image] =>[orig_patent_app_number] => 11327310 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/327310
Substrate processing apparatus and substrate processing method Jan 8, 2006 Issued
Array ( [id] => 281716 [patent_doc_number] => 07553716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-06-30 [patent_title] => 'Method for manufacturing a semiconductor thin film' [patent_app_type] => utility [patent_app_number] => 11/322653 [patent_app_country] => US [patent_app_date] => 2006-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 41 [patent_no_of_words] => 14818 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/553/07553716.pdf [firstpage_image] =>[orig_patent_app_number] => 11322653 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/322653
Method for manufacturing a semiconductor thin film Jan 2, 2006 Issued
Array ( [id] => 5116864 [patent_doc_number] => 20070138578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-21 [patent_title] => 'Metal oxynitride as a pFET material' [patent_app_type] => utility [patent_app_number] => 11/311455 [patent_app_country] => US [patent_app_date] => 2005-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5158 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20070138578.pdf [firstpage_image] =>[orig_patent_app_number] => 11311455 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/311455
Metal oxynitride as a pFET material Dec 18, 2005 Issued
Array ( [id] => 928490 [patent_doc_number] => 07314800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-01 [patent_title] => 'Application of different isolation schemes for logic and embedded memory' [patent_app_type] => utility [patent_app_number] => 11/296164 [patent_app_country] => US [patent_app_date] => 2005-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 32 [patent_no_of_words] => 8519 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/314/07314800.pdf [firstpage_image] =>[orig_patent_app_number] => 11296164 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/296164
Application of different isolation schemes for logic and embedded memory Dec 6, 2005 Issued
Array ( [id] => 826859 [patent_doc_number] => 07402524 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-22 [patent_title] => 'Post high voltage gate oxide pattern high-vacuum outgas surface treatment' [patent_app_type] => utility [patent_app_number] => 11/292883 [patent_app_country] => US [patent_app_date] => 2005-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4378 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/402/07402524.pdf [firstpage_image] =>[orig_patent_app_number] => 11292883 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/292883
Post high voltage gate oxide pattern high-vacuum outgas surface treatment Dec 1, 2005 Issued
Array ( [id] => 5715728 [patent_doc_number] => 20060079091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-13 [patent_title] => 'Mask, method of producing the same, and method of producing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/284902 [patent_app_country] => US [patent_app_date] => 2005-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6022 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20060079091.pdf [firstpage_image] =>[orig_patent_app_number] => 11284902 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/284902
Mask, method of producing the same, and method of producing semiconductor device Nov 22, 2005 Abandoned
Array ( [id] => 587443 [patent_doc_number] => 07446388 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-04 [patent_title] => 'Integrated thin film capacitor/inductor/interconnect system and method' [patent_app_type] => utility [patent_app_number] => 11/284704 [patent_app_country] => US [patent_app_date] => 2005-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6640 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/446/07446388.pdf [firstpage_image] =>[orig_patent_app_number] => 11284704 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/284704
Integrated thin film capacitor/inductor/interconnect system and method Nov 20, 2005 Issued
Array ( [id] => 574025 [patent_doc_number] => 07462907 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-12-09 [patent_title] => 'Method of increasing erase speed in memory arrays' [patent_app_type] => utility [patent_app_number] => 11/268025 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4727 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/462/07462907.pdf [firstpage_image] =>[orig_patent_app_number] => 11268025 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/268025
Method of increasing erase speed in memory arrays Nov 6, 2005 Issued
Array ( [id] => 5591042 [patent_doc_number] => 20060040494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-23 [patent_title] => 'Through-hole conductors for semiconductor substrates and method for making same' [patent_app_type] => utility [patent_app_number] => 11/256791 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4727 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20060040494.pdf [firstpage_image] =>[orig_patent_app_number] => 11256791 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/256791
Through-hole conductors for semiconductor substrates and method for making same Oct 23, 2005 Issued
Array ( [id] => 833158 [patent_doc_number] => 07396447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Through-hole conductors for semiconductor substrates and system for making same' [patent_app_type] => utility [patent_app_number] => 11/257215 [patent_app_country] => US [patent_app_date] => 2005-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4730 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/396/07396447.pdf [firstpage_image] =>[orig_patent_app_number] => 11257215 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/257215
Through-hole conductors for semiconductor substrates and system for making same Oct 23, 2005 Issued
Array ( [id] => 606343 [patent_doc_number] => 07153708 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-26 [patent_title] => 'Seed layer processes for MOCVD of ferroelectric thin films on high-k gate oxides' [patent_app_type] => utility [patent_app_number] => 11/249883 [patent_app_country] => US [patent_app_date] => 2005-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2044 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/153/07153708.pdf [firstpage_image] =>[orig_patent_app_number] => 11249883 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/249883
Seed layer processes for MOCVD of ferroelectric thin films on high-k gate oxides Oct 11, 2005 Issued
Array ( [id] => 5877978 [patent_doc_number] => 20060027818 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-09 [patent_title] => 'Diode having high brightness and method thereof' [patent_app_type] => utility [patent_app_number] => 11/247225 [patent_app_country] => US [patent_app_date] => 2005-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4146 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20060027818.pdf [firstpage_image] =>[orig_patent_app_number] => 11247225 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/247225
Diode having high brightness and method thereof Oct 11, 2005 Issued
Array ( [id] => 5727014 [patent_doc_number] => 20060057774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-16 [patent_title] => 'Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages' [patent_app_type] => utility [patent_app_number] => 11/248914 [patent_app_country] => US [patent_app_date] => 2005-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4883 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20060057774.pdf [firstpage_image] =>[orig_patent_app_number] => 11248914 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/248914
Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages Oct 10, 2005 Issued
Array ( [id] => 5810787 [patent_doc_number] => 20060081895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Semiconductor device having fin transistor and planar transistor and associated methods of manufacture' [patent_app_type] => utility [patent_app_number] => 11/244136 [patent_app_country] => US [patent_app_date] => 2005-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20060081895.pdf [firstpage_image] =>[orig_patent_app_number] => 11244136 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/244136
Semiconductor device having fin transistor and planar transistor and associated methods of manufacture Oct 5, 2005 Issued
Array ( [id] => 366524 [patent_doc_number] => 07479413 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-01-20 [patent_title] => 'Method for fabricating semiconductor package with circuit side polymer layer' [patent_app_type] => utility [patent_app_number] => 11/242224 [patent_app_country] => US [patent_app_date] => 2005-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 30 [patent_no_of_words] => 5800 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/479/07479413.pdf [firstpage_image] =>[orig_patent_app_number] => 11242224 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/242224
Method for fabricating semiconductor package with circuit side polymer layer Oct 2, 2005 Issued
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