Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7169243 [patent_doc_number] => 20050121787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 11/002295 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9982 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20050121787.pdf [firstpage_image] =>[orig_patent_app_number] => 11002295 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/002295
Semiconductor device and method for manufacturing the same Dec 2, 2004 Issued
Array ( [id] => 418761 [patent_doc_number] => 07276433 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-02 [patent_title] => 'Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors' [patent_app_type] => utility [patent_app_number] => 11/003275 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/276/07276433.pdf [firstpage_image] =>[orig_patent_app_number] => 11003275 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/003275
Methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors Dec 2, 2004 Issued
Array ( [id] => 5895043 [patent_doc_number] => 20060003582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/002706 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8707 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003582.pdf [firstpage_image] =>[orig_patent_app_number] => 11002706 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/002706
Method for fabricating semiconductor device Dec 2, 2004 Issued
Array ( [id] => 428627 [patent_doc_number] => 07268061 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-09-11 [patent_title] => 'Substrate attaching method' [patent_app_type] => utility [patent_app_number] => 11/001575 [patent_app_country] => US [patent_app_date] => 2004-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2459 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/268/07268061.pdf [firstpage_image] =>[orig_patent_app_number] => 11001575 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/001575
Substrate attaching method Nov 30, 2004 Issued
Array ( [id] => 377020 [patent_doc_number] => 07312120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-25 [patent_title] => 'Method for obtaining extreme selectivity of metal nitrides and metal oxides' [patent_app_type] => utility [patent_app_number] => 11/000825 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4921 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/312/07312120.pdf [firstpage_image] =>[orig_patent_app_number] => 11000825 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000825
Method for obtaining extreme selectivity of metal nitrides and metal oxides Nov 29, 2004 Issued
Array ( [id] => 7104069 [patent_doc_number] => 20050106795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-19 [patent_title] => 'Methods of forming field effect transistors and methods of forming field effect transistor gates and gate lines' [patent_app_type] => utility [patent_app_number] => 11/000809 [patent_app_country] => US [patent_app_date] => 2004-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3721 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20050106795.pdf [firstpage_image] =>[orig_patent_app_number] => 11000809 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/000809
Method of forming a field effect transistor Nov 29, 2004 Issued
Array ( [id] => 383057 [patent_doc_number] => 07307009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Phosphoric acid free process for polysilicon gate definition' [patent_app_type] => utility [patent_app_number] => 10/999270 [patent_app_country] => US [patent_app_date] => 2004-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1840 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307009.pdf [firstpage_image] =>[orig_patent_app_number] => 10999270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/999270
Phosphoric acid free process for polysilicon gate definition Nov 28, 2004 Issued
Array ( [id] => 6923427 [patent_doc_number] => 20050236682 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Method of manufacturing MEMS device' [patent_app_type] => utility [patent_app_number] => 10/995406 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4266 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0236/20050236682.pdf [firstpage_image] =>[orig_patent_app_number] => 10995406 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/995406
Method of manufacturing MEMS device Nov 23, 2004 Issued
Array ( [id] => 267074 [patent_doc_number] => 07566599 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-07-28 [patent_title] => 'High performance FET with elevated source/drain region' [patent_app_type] => utility [patent_app_number] => 10/996866 [patent_app_country] => US [patent_app_date] => 2004-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 2807 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/566/07566599.pdf [firstpage_image] =>[orig_patent_app_number] => 10996866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/996866
High performance FET with elevated source/drain region Nov 23, 2004 Issued
Array ( [id] => 404615 [patent_doc_number] => 07288444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-30 [patent_title] => 'Thin film transistor and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/994265 [patent_app_country] => US [patent_app_date] => 2004-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 34 [patent_no_of_words] => 3941 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/288/07288444.pdf [firstpage_image] =>[orig_patent_app_number] => 10994265 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/994265
Thin film transistor and method of manufacturing the same Nov 22, 2004 Issued
Array ( [id] => 6991885 [patent_doc_number] => 20050090922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-28 [patent_title] => 'Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit' [patent_app_type] => utility [patent_app_number] => 10/989355 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10383 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20050090922.pdf [firstpage_image] =>[orig_patent_app_number] => 10989355 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/989355
Test circuit, semiconductor product wafer having the test circuit, and method of monitoring manufacturing process using the test circuit Nov 16, 2004 Abandoned
Array ( [id] => 7144191 [patent_doc_number] => 20050118754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Method for fabricating semiconductor devices using strained silicon bearing material' [patent_app_type] => utility [patent_app_number] => 10/992596 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3642 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20050118754.pdf [firstpage_image] =>[orig_patent_app_number] => 10992596 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/992596
Method for fabricating semiconductor devices using strained silicon bearing material Nov 16, 2004 Issued
Array ( [id] => 895113 [patent_doc_number] => 07341930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-11 [patent_title] => 'Systems and methods for integration of heterogeneous circuit devices' [patent_app_type] => utility [patent_app_number] => 10/990711 [patent_app_country] => US [patent_app_date] => 2004-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 3818 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/341/07341930.pdf [firstpage_image] =>[orig_patent_app_number] => 10990711 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/990711
Systems and methods for integration of heterogeneous circuit devices Nov 16, 2004 Issued
Array ( [id] => 7005259 [patent_doc_number] => 20050170572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Laser annealing apparatus and annealing method of semiconductor thin film using the same' [patent_app_type] => utility [patent_app_number] => 10/986936 [patent_app_country] => US [patent_app_date] => 2004-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10570 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20050170572.pdf [firstpage_image] =>[orig_patent_app_number] => 10986936 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/986936
Laser annealing apparatus and annealing method of semiconductor thin film using the same Nov 14, 2004 Issued
Array ( [id] => 6981070 [patent_doc_number] => 20050151138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Methods of processing semiconductor wafer backsides having light emitting devices (LEDS) thereon and leds so formed' [patent_app_type] => utility [patent_app_number] => 10/987135 [patent_app_country] => US [patent_app_date] => 2004-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5433 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0151/20050151138.pdf [firstpage_image] =>[orig_patent_app_number] => 10987135 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/987135
Methods of processing semiconductor wafer backsides having light emitting devices (LEDs) thereon Nov 11, 2004 Issued
Array ( [id] => 411505 [patent_doc_number] => 07282389 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-16 [patent_title] => 'Semiconductor device manufacturing method and manufacturing apparatus' [patent_app_type] => utility [patent_app_number] => 10/985666 [patent_app_country] => US [patent_app_date] => 2004-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5923 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/282/07282389.pdf [firstpage_image] =>[orig_patent_app_number] => 10985666 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/985666
Semiconductor device manufacturing method and manufacturing apparatus Nov 10, 2004 Issued
Array ( [id] => 7235916 [patent_doc_number] => 20050139893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Non-volatile flash semiconductor memory and fabrication method' [patent_app_type] => utility [patent_app_number] => 10/991345 [patent_app_country] => US [patent_app_date] => 2004-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2126 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20050139893.pdf [firstpage_image] =>[orig_patent_app_number] => 10991345 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/991345
Non-volatile flash semiconductor memory and fabrication method Nov 8, 2004 Issued
Array ( [id] => 383052 [patent_doc_number] => 07307004 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-11 [patent_title] => 'Method with mechanically strained silicon for enhancing speed of integrated circuits or devices' [patent_app_type] => utility [patent_app_number] => 10/982375 [patent_app_country] => US [patent_app_date] => 2004-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 3563 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/307/07307004.pdf [firstpage_image] =>[orig_patent_app_number] => 10982375 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982375
Method with mechanically strained silicon for enhancing speed of integrated circuits or devices Nov 4, 2004 Issued
Array ( [id] => 5807839 [patent_doc_number] => 20060094194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology' [patent_app_type] => utility [patent_app_number] => 10/982115 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2904 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20060094194.pdf [firstpage_image] =>[orig_patent_app_number] => 10982115 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982115
Advanced disposable spacer process by low-temperature high-stress nitride film for sub-90NM CMOS technology Nov 3, 2004 Abandoned
Array ( [id] => 482593 [patent_doc_number] => 07220636 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-22 [patent_title] => 'Process for controlling performance characteristics of a negative differential resistance (NDR) device' [patent_app_type] => utility [patent_app_number] => 10/982425 [patent_app_country] => US [patent_app_date] => 2004-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 14803 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/220/07220636.pdf [firstpage_image] =>[orig_patent_app_number] => 10982425 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/982425
Process for controlling performance characteristics of a negative differential resistance (NDR) device Nov 3, 2004 Issued
Menu