Search

Laura Mary Menz

Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )

Most Active Art Unit
2813
Art Unit(s)
2813
Total Applications
2324
Issued Applications
1995
Pending Applications
138
Abandoned Applications
216

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7189793 [patent_doc_number] => 20040084745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Systems and methods for integration of heterogeneous circuit devices' [patent_app_type] => new [patent_app_number] => 10/727692 [patent_app_country] => US [patent_app_date] => 2003-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 3832 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20040084745.pdf [firstpage_image] =>[orig_patent_app_number] => 10727692 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/727692
Systems and methods for integration of heterogeneous circuit devices Dec 3, 2003 Issued
Array ( [id] => 5874563 [patent_doc_number] => 20060166464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-27 [patent_title] => 'Method and device for machining a wafer, in addition to a wafer comprising a separation layer and a support layer' [patent_app_type] => utility [patent_app_number] => 10/536725 [patent_app_country] => US [patent_app_date] => 2003-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 13134 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0166/20060166464.pdf [firstpage_image] =>[orig_patent_app_number] => 10536725 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/536725
Method and device for machining a wafer, in addition to a wafer comprising a separation layer and a support layer Nov 27, 2003 Issued
Array ( [id] => 7304928 [patent_doc_number] => 20040115889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-17 [patent_title] => 'Ultra shallow junction formation' [patent_app_type] => new [patent_app_number] => 10/721985 [patent_app_country] => US [patent_app_date] => 2003-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1946 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20040115889.pdf [firstpage_image] =>[orig_patent_app_number] => 10721985 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/721985
Ultra shallow junction formation Nov 24, 2003 Abandoned
Array ( [id] => 7295767 [patent_doc_number] => 20040124412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Misalignment test structure and method thereof' [patent_app_type] => new [patent_app_number] => 10/718612 [patent_app_country] => US [patent_app_date] => 2003-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20040124412.pdf [firstpage_image] =>[orig_patent_app_number] => 10718612 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/718612
Misalignment test structure and method thereof Nov 23, 2003 Issued
Array ( [id] => 7451448 [patent_doc_number] => 20040099899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'High K dielectric material and method of making a high K dielectric material' [patent_app_type] => new [patent_app_number] => 10/718536 [patent_app_country] => US [patent_app_date] => 2003-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1450 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20040099899.pdf [firstpage_image] =>[orig_patent_app_number] => 10718536 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/718536
High K dielectric material and method of making a high K dielectric material Nov 23, 2003 Issued
Array ( [id] => 7466726 [patent_doc_number] => 20040101997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Method for fabricating thin film transistor' [patent_app_type] => new [patent_app_number] => 10/713219 [patent_app_country] => US [patent_app_date] => 2003-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11928 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20040101997.pdf [firstpage_image] =>[orig_patent_app_number] => 10713219 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713219
Method for fabricating thin film transistor Nov 16, 2003 Issued
Array ( [id] => 514990 [patent_doc_number] => 07192849 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Methods of growing nitride-based film using varying pulses' [patent_app_type] => utility [patent_app_number] => 10/713326 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3408 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/192/07192849.pdf [firstpage_image] =>[orig_patent_app_number] => 10713326 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/713326
Methods of growing nitride-based film using varying pulses Nov 13, 2003 Issued
Array ( [id] => 7002482 [patent_doc_number] => 20050167795 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Electronic devices and its production methods' [patent_app_type] => utility [patent_app_number] => 10/706912 [patent_app_country] => US [patent_app_date] => 2003-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12332 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0167/20050167795.pdf [firstpage_image] =>[orig_patent_app_number] => 10706912 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706912
Electronic devices and its production methods Nov 13, 2003 Issued
Array ( [id] => 7471969 [patent_doc_number] => 20040097027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Method for manufacturing semiconductor device' [patent_app_type] => new [patent_app_number] => 10/712716 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4383 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20040097027.pdf [firstpage_image] =>[orig_patent_app_number] => 10712716 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712716
Method for manufacturing semiconductor device Nov 12, 2003 Abandoned
Array ( [id] => 526721 [patent_doc_number] => 07187119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Methods and structures for reducing lateral diffusion through cooperative barrier layers' [patent_app_type] => utility [patent_app_number] => 10/712492 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 4221 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187119.pdf [firstpage_image] =>[orig_patent_app_number] => 10712492 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712492
Methods and structures for reducing lateral diffusion through cooperative barrier layers Nov 12, 2003 Issued
Array ( [id] => 518299 [patent_doc_number] => 07189659 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-13 [patent_title] => 'Method for fabricating a semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/705881 [patent_app_country] => US [patent_app_date] => 2003-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 7982 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/189/07189659.pdf [firstpage_image] =>[orig_patent_app_number] => 10705881 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/705881
Method for fabricating a semiconductor device Nov 12, 2003 Issued
Array ( [id] => 7408639 [patent_doc_number] => 20040106236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-03 [patent_title] => 'Method to manufacture LDMOS transistors with improved threshold voltage control' [patent_app_type] => new [patent_app_number] => 10/712455 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2257 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20040106236.pdf [firstpage_image] =>[orig_patent_app_number] => 10712455 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/712455
Method to manufacture LDMOS transistors with improved threshold voltage control Nov 11, 2003 Issued
Array ( [id] => 887740 [patent_doc_number] => 07348187 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-03-25 [patent_title] => 'Method, device, computer-readable storage medium and computer program element for the monitoring of a manufacturing process of a plurality of physical objects' [patent_app_type] => utility [patent_app_number] => 10/706612 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4714 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/348/07348187.pdf [firstpage_image] =>[orig_patent_app_number] => 10706612 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706612
Method, device, computer-readable storage medium and computer program element for the monitoring of a manufacturing process of a plurality of physical objects Nov 11, 2003 Issued
Array ( [id] => 6905715 [patent_doc_number] => 20050101110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Novel method to reduce the fluorine contamination on the Al/Al-Cu pad by a post high cathod temperature plasma treatment' [patent_app_type] => utility [patent_app_number] => 10/706382 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2568 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20050101110.pdf [firstpage_image] =>[orig_patent_app_number] => 10706382 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/706382
Method to reduce the fluorine contamination on the Al/Al-Cu pad by a post high cathod temperature plasma treatment Nov 11, 2003 Issued
Array ( [id] => 7443172 [patent_doc_number] => 20040185670 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-23 [patent_title] => 'Processing system and method for treating a substrate' [patent_app_type] => new [patent_app_number] => 10/705201 [patent_app_country] => US [patent_app_date] => 2003-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9252 [patent_no_of_claims] => 66 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20040185670.pdf [firstpage_image] =>[orig_patent_app_number] => 10705201 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/705201
Processing system and method for treating a substrate Nov 11, 2003 Issued
Array ( [id] => 526277 [patent_doc_number] => 07187072 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'Fabrication process of semiconductor package and semiconductor package' [patent_app_type] => utility [patent_app_number] => 10/705706 [patent_app_country] => US [patent_app_date] => 2003-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 133 [patent_no_of_words] => 15646 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/187/07187072.pdf [firstpage_image] =>[orig_patent_app_number] => 10705706 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/705706
Fabrication process of semiconductor package and semiconductor package Nov 9, 2003 Issued
Array ( [id] => 7318817 [patent_doc_number] => 20040135168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor' [patent_app_type] => new [patent_app_number] => 10/703921 [patent_app_country] => US [patent_app_date] => 2003-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11834 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20040135168.pdf [firstpage_image] =>[orig_patent_app_number] => 10703921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/703921
Power semiconductor switching devices, power converters, integrated circuit assemblies, integrated circuitry, power current switching methods, methods of forming a power semiconductor switching device, power conversion methods, power semiconductor switching device packaging methods, and methods of forming a power transistor Nov 6, 2003 Issued
Array ( [id] => 6903385 [patent_doc_number] => 20050098780 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Planar voltage contrast test structure and method' [patent_app_type] => utility [patent_app_number] => 10/703285 [patent_app_country] => US [patent_app_date] => 2003-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5289 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20050098780.pdf [firstpage_image] =>[orig_patent_app_number] => 10703285 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/703285
Planar voltage contrast test structure and method Nov 5, 2003 Issued
Array ( [id] => 7466697 [patent_doc_number] => 20040101991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-27 [patent_title] => 'Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages' [patent_app_type] => new [patent_app_number] => 10/701128 [patent_app_country] => US [patent_app_date] => 2003-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4948 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20040101991.pdf [firstpage_image] =>[orig_patent_app_number] => 10701128 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/701128
Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages Nov 2, 2003 Issued
Array ( [id] => 953843 [patent_doc_number] => 06958256 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Process for the back-surface grinding of wafers' [patent_app_type] => utility [patent_app_number] => 10/696866 [patent_app_country] => US [patent_app_date] => 2003-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4096 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/958/06958256.pdf [firstpage_image] =>[orig_patent_app_number] => 10696866 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/696866
Process for the back-surface grinding of wafers Oct 29, 2003 Issued
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