
Laura Mary Menz
Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813 |
| Total Applications | 2324 |
| Issued Applications | 1995 |
| Pending Applications | 138 |
| Abandoned Applications | 216 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6988697
[patent_doc_number] => 20050087810
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Application of different isolation schemes for logic and embedded memory'
[patent_app_type] => utility
[patent_app_number] => 10/694237
[patent_app_country] => US
[patent_app_date] => 2003-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 8496
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20050087810.pdf
[firstpage_image] =>[orig_patent_app_number] => 10694237
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/694237 | Application of different isolation schemes for logic and embedded memory | Oct 26, 2003 | Issued |
Array
(
[id] => 7324220
[patent_doc_number] => 20040137700
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-15
[patent_title] => 'Method for dividing semiconductor wafer'
[patent_app_type] => new
[patent_app_number] => 10/475676
[patent_app_country] => US
[patent_app_date] => 2003-10-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4416
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0137/20040137700.pdf
[firstpage_image] =>[orig_patent_app_number] => 10475676
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/475676 | Method for dividing semiconductor wafer | Oct 22, 2003 | Abandoned |
Array
(
[id] => 7383511
[patent_doc_number] => 20040082175
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-29
[patent_title] => 'Process for high-dielectric constant metal-insulator metal capacitor in VLSI multi-level metallization systems'
[patent_app_type] => new
[patent_app_number] => 10/690730
[patent_app_country] => US
[patent_app_date] => 2003-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2656
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0082/20040082175.pdf
[firstpage_image] =>[orig_patent_app_number] => 10690730
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/690730 | Process for high-dielectric constant metal-insulator metal capacitor in VLSI multi-level metallization systems | Oct 21, 2003 | Abandoned |
Array
(
[id] => 6988733
[patent_doc_number] => 20050087836
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-28
[patent_title] => 'Electrically programmable polysilicon fuse with multiple level resistance and programming'
[patent_app_type] => utility
[patent_app_number] => 10/690995
[patent_app_country] => US
[patent_app_date] => 2003-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3708
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0087/20050087836.pdf
[firstpage_image] =>[orig_patent_app_number] => 10690995
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/690995 | Electrically programmable polysilicon fuse with multiple level resistance and programming | Oct 21, 2003 | Abandoned |
Array
(
[id] => 7472107
[patent_doc_number] => 20040097054
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-20
[patent_title] => 'Fabrication method of semiconductor circuit device'
[patent_app_type] => new
[patent_app_number] => 10/688992
[patent_app_country] => US
[patent_app_date] => 2003-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8584
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0097/20040097054.pdf
[firstpage_image] =>[orig_patent_app_number] => 10688992
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/688992 | Fabrication method of semiconductor circuit device | Oct 20, 2003 | Issued |
Array
(
[id] => 7162122
[patent_doc_number] => 20050085092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Multi-layer dielectric containing diffusion barrier material'
[patent_app_type] => utility
[patent_app_number] => 10/687271
[patent_app_country] => US
[patent_app_date] => 2003-10-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2973
[patent_no_of_claims] => 42
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20050085092.pdf
[firstpage_image] =>[orig_patent_app_number] => 10687271
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/687271 | Multi-layer dielectric containing diffusion barrier material | Oct 15, 2003 | Issued |
Array
(
[id] => 7162012
[patent_doc_number] => 20050085054
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion'
[patent_app_type] => utility
[patent_app_number] => 10/684596
[patent_app_country] => US
[patent_app_date] => 2003-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 2872
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0085/20050085054.pdf
[firstpage_image] =>[orig_patent_app_number] => 10684596
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/684596 | Deposition of carbon and nitrogen doped poly silicon films, and retarded boron diffusion and improved poly depletion | Oct 14, 2003 | Issued |
Array
(
[id] => 7289661
[patent_doc_number] => 20040110315
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Apparatus for evaluating amount of charge, method for fabricating the same, and method for evaluating amount of charge'
[patent_app_type] => new
[patent_app_number] => 10/684465
[patent_app_country] => US
[patent_app_date] => 2003-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 6729
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 49
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20040110315.pdf
[firstpage_image] =>[orig_patent_app_number] => 10684465
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/684465 | Apparatus for evaluating amount of charge, method for fabricating the same, and method for evaluating amount of charge | Oct 14, 2003 | Issued |
Array
(
[id] => 7609493
[patent_doc_number] => 06998696
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-14
[patent_title] => 'Integrated thin film capacitor/inductor/interconnect system and method'
[patent_app_type] => utility
[patent_app_number] => 10/686116
[patent_app_country] => US
[patent_app_date] => 2003-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6670
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/998/06998696.pdf
[firstpage_image] =>[orig_patent_app_number] => 10686116
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/686116 | Integrated thin film capacitor/inductor/interconnect system and method | Oct 14, 2003 | Issued |
Array
(
[id] => 542116
[patent_doc_number] => 07169683
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-01-30
[patent_title] => 'Preventive treatment method for a multilayer semiconductor structure'
[patent_app_type] => utility
[patent_app_number] => 10/686082
[patent_app_country] => US
[patent_app_date] => 2003-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 9
[patent_no_of_words] => 6419
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/169/07169683.pdf
[firstpage_image] =>[orig_patent_app_number] => 10686082
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/686082 | Preventive treatment method for a multilayer semiconductor structure | Oct 13, 2003 | Issued |
Array
(
[id] => 7301263
[patent_doc_number] => 20040113240
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-17
[patent_title] => 'An electronic component with a leadframe'
[patent_app_type] => new
[patent_app_number] => 10/685308
[patent_app_country] => US
[patent_app_date] => 2003-10-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 1631
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0113/20040113240.pdf
[firstpage_image] =>[orig_patent_app_number] => 10685308
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/685308 | An electronic component with a leadframe | Oct 13, 2003 | Abandoned |
Array
(
[id] => 963631
[patent_doc_number] => 06949443
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-09-27
[patent_title] => 'High performance semiconductor devices fabricated with strain-induced processes and methods for making same'
[patent_app_type] => utility
[patent_app_number] => 10/683901
[patent_app_country] => US
[patent_app_date] => 2003-10-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 15
[patent_no_of_words] => 4318
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/949/06949443.pdf
[firstpage_image] =>[orig_patent_app_number] => 10683901
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/683901 | High performance semiconductor devices fabricated with strain-induced processes and methods for making same | Oct 9, 2003 | Issued |
Array
(
[id] => 7211141
[patent_doc_number] => 20040071034
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-04-15
[patent_title] => 'Electrically isolated pillars in active devices'
[patent_app_type] => new
[patent_app_number] => 10/681507
[patent_app_country] => US
[patent_app_date] => 2003-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 7480
[patent_no_of_claims] => 70
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0071/20040071034.pdf
[firstpage_image] =>[orig_patent_app_number] => 10681507
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/681507 | Electrically isolated pillars in active devices | Oct 6, 2003 | Issued |
Array
(
[id] => 707016
[patent_doc_number] => 07060339
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-13
[patent_title] => 'Dicing/die-bonding film, method of fixing chipped work and semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/678855
[patent_app_country] => US
[patent_app_date] => 2003-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 10766
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/060/07060339.pdf
[firstpage_image] =>[orig_patent_app_number] => 10678855
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/678855 | Dicing/die-bonding film, method of fixing chipped work and semiconductor device | Oct 2, 2003 | Issued |
Array
(
[id] => 504937
[patent_doc_number] => 07202169
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-10
[patent_title] => 'Method and system for etching high-k dielectric materials'
[patent_app_type] => utility
[patent_app_number] => 10/670795
[patent_app_country] => US
[patent_app_date] => 2003-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 32
[patent_no_of_words] => 10301
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/202/07202169.pdf
[firstpage_image] =>[orig_patent_app_number] => 10670795
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/670795 | Method and system for etching high-k dielectric materials | Sep 25, 2003 | Issued |
Array
(
[id] => 7287716
[patent_doc_number] => 20040109250
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-06-10
[patent_title] => 'Tunable-wavelength optical filter and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/671825
[patent_app_country] => US
[patent_app_date] => 2003-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4884
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0109/20040109250.pdf
[firstpage_image] =>[orig_patent_app_number] => 10671825
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/671825 | Tunable-wavelength optical filter and method of manufacturing the same | Sep 24, 2003 | Issued |
Array
(
[id] => 334622
[patent_doc_number] => 07508034
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-24
[patent_title] => 'Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/668186
[patent_app_country] => US
[patent_app_date] => 2003-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 66
[patent_no_of_words] => 35069
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/508/07508034.pdf
[firstpage_image] =>[orig_patent_app_number] => 10668186
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/668186 | Single-crystal silicon substrate, SOI substrate, semiconductor device, display device, and manufacturing method of semiconductor device | Sep 23, 2003 | Issued |
Array
(
[id] => 7335391
[patent_doc_number] => 20040132235
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-07-08
[patent_title] => 'Silicon thin film transistor, a method of manufacture, and a display screen'
[patent_app_type] => new
[patent_app_number] => 10/668877
[patent_app_country] => US
[patent_app_date] => 2003-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3618
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 31
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0132/20040132235.pdf
[firstpage_image] =>[orig_patent_app_number] => 10668877
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/668877 | Silicon thin film transistor, a method of manufacture, and a display screen | Sep 22, 2003 | Abandoned |
Array
(
[id] => 500004
[patent_doc_number] => 07205165
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-04-17
[patent_title] => 'Method for determining the reliability of dielectric layers'
[patent_app_type] => utility
[patent_app_number] => 10/664665
[patent_app_country] => US
[patent_app_date] => 2003-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5539
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/205/07205165.pdf
[firstpage_image] =>[orig_patent_app_number] => 10664665
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/664665 | Method for determining the reliability of dielectric layers | Sep 17, 2003 | Issued |
Array
(
[id] => 7429282
[patent_doc_number] => 20040266078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-12-30
[patent_title] => 'Method of fabricating polycrystalline silicon thin film for improving crystallization characteristics and method of fabricating liquid crystal display device using the same'
[patent_app_type] => new
[patent_app_number] => 10/661486
[patent_app_country] => US
[patent_app_date] => 2003-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7122
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0266/20040266078.pdf
[firstpage_image] =>[orig_patent_app_number] => 10661486
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/661486 | Method of fabricating polycrystalline silicon thin film for improving crystallization characteristics and method of fabricating liquid crystal display device using the same | Sep 14, 2003 | Issued |