Laura Mary Menz

Array ( [id] => 7465219 [patent_doc_number] => 20040053452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-18 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 10/659346 [patent_app_country] => US [patent_app_date] => 2003-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7282 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20040053452.pdf [firstpage_image] =>[orig_patent_app_number] => 10659346 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 793179 [patent_doc_number] => 06982225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Interposer and method of making same' [patent_app_type] => utility [patent_app_number] => 10/660421 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 7233 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982225.pdf [firstpage_image] =>[orig_patent_app_number] => 10660421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 732814 [patent_doc_number] => 07037863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Post thermal treatment methods of forming high dielectric layers over interfacial layers in integrated circuit devices' [patent_app_type] => utility [patent_app_number] => 10/659945 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 7100 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/037/07037863.pdf [firstpage_image] =>[orig_patent_app_number] => 10659945 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 725696 [patent_doc_number] => 07045836 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Semiconductor structure having a strained region and a method of fabricating same' [patent_app_type] => utility [patent_app_number] => 10/657616 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4393 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/045/07045836.pdf [firstpage_image] =>[orig_patent_app_number] => 10657616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7471252 [patent_doc_number] => 20040121504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Process for the fabrication of an inertial sensor with failure threshold' [patent_app_type] => new [patent_app_number] => 10/650275 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5193 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0121/20040121504.pdf [firstpage_image] =>[orig_patent_app_number] => 10650275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7287249 [patent_doc_number] => 20040147074 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-29 [patent_title] => 'Method for fabricating a storage capacitor' [patent_app_type] => new [patent_app_number] => 10/650055 [patent_app_country] => US [patent_app_date] => 2003-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8354 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0147/20040147074.pdf [firstpage_image] =>[orig_patent_app_number] => 10650055 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 616382 [patent_doc_number] => 07144793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'Method of producing crystalline semiconductor material and method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/645805 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 36 [patent_no_of_words] => 9805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/144/07144793.pdf [firstpage_image] =>[orig_patent_app_number] => 10645805 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7241925 [patent_doc_number] => 20050073022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Shallow trench isolation (STI) region with high-K liner and method of formation' [patent_app_type] => utility [patent_app_number] => 10/642916 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4629 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20050073022.pdf [firstpage_image] =>[orig_patent_app_number] => 10642916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7459085 [patent_doc_number] => 20040094768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-20 [patent_title] => 'Methods for producing full-color organic electroluminescent devices' [patent_app_type] => new [patent_app_number] => 10/643255 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7789 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20040094768.pdf [firstpage_image] =>[orig_patent_app_number] => 10643255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5916415 [patent_doc_number] => 20060237740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-26 [patent_title] => 'Mbe growth of an algan layer or algan multilayer structure' [patent_app_type] => utility [patent_app_number] => 10/525406 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5835 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0237/20060237740.pdf [firstpage_image] =>[orig_patent_app_number] => 10525406 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7031086 [patent_doc_number] => 20050029659 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Low resistance and reliable copper interconnects by variable doping' [patent_app_type] => utility [patent_app_number] => 10/637105 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20050029659.pdf [firstpage_image] =>[orig_patent_app_number] => 10637105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7147941 [patent_doc_number] => 20050023656 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Vertical system integration' [patent_app_type] => utility [patent_app_number] => 10/485046 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 82193 [patent_no_of_claims] => 102 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20050023656.pdf [firstpage_image] =>[orig_patent_app_number] => 10485046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7147776 [patent_doc_number] => 20050023605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'High voltage semiconductor device having an increased breakdown voltage relative to its on-resistance' [patent_app_type] => utility [patent_app_number] => 10/631081 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2634 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20050023605.pdf [firstpage_image] =>[orig_patent_app_number] => 10631081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 958805 [patent_doc_number] => 06953751 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Micro device and process for producing it' [patent_app_type] => utility [patent_app_number] => 10/631421 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2025 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/953/06953751.pdf [firstpage_image] =>[orig_patent_app_number] => 10631421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7398763 [patent_doc_number] => 20040018671 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-29 [patent_title] => 'Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and integrated circuitry' [patent_app_type] => new [patent_app_number] => 10/630427 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4908 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20040018671.pdf [firstpage_image] =>[orig_patent_app_number] => 10630427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 944111 [patent_doc_number] => 06967165 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-22 [patent_title] => 'Method for fabricating multilayer interconnect and method for checking the same' [patent_app_type] => utility [patent_app_number] => 10/628451 [patent_app_country] => US [patent_app_date] => 2003-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 6965 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/967/06967165.pdf [firstpage_image] =>[orig_patent_app_number] => 10628451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 701486 [patent_doc_number] => 07064032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method for forming non-volatile memory cell with low-temperature-formed dielectric between word and bit lines, and non-volatile memory array including such memory cells' [patent_app_type] => utility [patent_app_number] => 10/627000 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 4823 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064032.pdf [firstpage_image] =>[orig_patent_app_number] => 10627000 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6903425 [patent_doc_number] => 20050098820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Method to remove an oxide seam along gate stack edge, when nitride space formation begins with an oxide liner surrounding gate stack' [patent_app_type] => utility [patent_app_number] => 10/626620 [patent_app_country] => US [patent_app_date] => 2003-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4101 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0098/20050098820.pdf [firstpage_image] =>[orig_patent_app_number] => 10626620 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7022922 [patent_doc_number] => 20050017316 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'CMOS image sensor device and method' [patent_app_type] => utility [patent_app_number] => 10/626061 [patent_app_country] => US [patent_app_date] => 2003-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3301 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20050017316.pdf [firstpage_image] =>[orig_patent_app_number] => 10626061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7252845 [patent_doc_number] => 20050074933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-07 [patent_title] => 'Phase change material memory device' [patent_app_type] => utility [patent_app_number] => 10/623861 [patent_app_country] => US [patent_app_date] => 2003-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1811 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20050074933.pdf [firstpage_image] =>[orig_patent_app_number] => 10623861 [rel_patent_id] =>[rel_patent_doc_number] =>)