
Laura Mary Menz
Examiner (ID: 7325, Phone: (571)272-1697 , Office: P/2813 )
| Most Active Art Unit | 2813 |
| Art Unit(s) | 2813 |
| Total Applications | 2324 |
| Issued Applications | 1995 |
| Pending Applications | 138 |
| Abandoned Applications | 216 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7631963
[patent_doc_number] => 06665374
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-16
[patent_title] => 'Active matrix substrate, method of manufacturing same, and flat-panel image sensor'
[patent_app_type] => B2
[patent_app_number] => 10/227804
[patent_app_country] => US
[patent_app_date] => 2002-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
[patent_figures_cnt] => 28
[patent_no_of_words] => 19519
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/665/06665374.pdf
[firstpage_image] =>[orig_patent_app_number] => 10227804
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/227804 | Active matrix substrate, method of manufacturing same, and flat-panel image sensor | Aug 26, 2002 | Issued |
Array
(
[id] => 6327484
[patent_doc_number] => 20020197848
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-26
[patent_title] => 'Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and integrated circuitry'
[patent_app_type] => new
[patent_app_number] => 10/227500
[patent_app_country] => US
[patent_app_date] => 2002-08-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 4903
[patent_no_of_claims] => 39
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0197/20020197848.pdf
[firstpage_image] =>[orig_patent_app_number] => 10227500
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/227500 | Semiconductor processing methods of forming integrated circuitry, forming conductive lines, forming a conductive grid, forming a conductive network, forming an electrical interconnection to a node location, forming an electrical interconnection with a transistor source/drain region, and integrated circuitry | Aug 21, 2002 | Abandoned |
Array
(
[id] => 6686368
[patent_doc_number] => 20030030091
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-13
[patent_title] => 'Dynamic random access memory trench capacitors'
[patent_app_type] => new
[patent_app_number] => 10/218007
[patent_app_country] => US
[patent_app_date] => 2002-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 4621
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0030/20030030091.pdf
[firstpage_image] =>[orig_patent_app_number] => 10218007
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/218007 | Dynamic random access memory trench capacitors | Aug 12, 2002 | Issued |
Array
(
[id] => 1257236
[patent_doc_number] => 06667518
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2003-12-23
[patent_title] => 'Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices'
[patent_app_type] => B2
[patent_app_number] => 10/215763
[patent_app_country] => US
[patent_app_date] => 2002-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_no_of_words] => 3426
[patent_no_of_claims] => 10
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[pdf_file] => patents/06/667/06667518.pdf
[firstpage_image] =>[orig_patent_app_number] => 10215763
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/215763 | Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices | Aug 8, 2002 | Issued |
Array
(
[id] => 6688165
[patent_doc_number] => 20030031890
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-02-13
[patent_title] => 'Angular substrates'
[patent_app_type] => new
[patent_app_number] => 10/214113
[patent_app_country] => US
[patent_app_date] => 2002-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3331
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0031/20030031890.pdf
[firstpage_image] =>[orig_patent_app_number] => 10214113
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/214113 | Angular substrates | Aug 7, 2002 | Issued |
Array
(
[id] => 6912492
[patent_doc_number] => 20050176250
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-08-11
[patent_title] => 'Polishig fluid for metallic films and method for producing semiconductor substrate using the same'
[patent_app_type] => utility
[patent_app_number] => 10/486726
[patent_app_country] => US
[patent_app_date] => 2002-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_no_of_words] => 13116
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[pdf_file] => publications/A1/0176/20050176250.pdf
[firstpage_image] =>[orig_patent_app_number] => 10486726
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/486726 | Polishig fluid for metallic films and method for producing semiconductor substrate using the same | Aug 7, 2002 | Abandoned |
Array
(
[id] => 338001
[patent_doc_number] => 07504342
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-03-17
[patent_title] => 'Photolithography method for fabricating thin film'
[patent_app_type] => utility
[patent_app_number] => 10/210109
[patent_app_country] => US
[patent_app_date] => 2002-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
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[patent_no_of_words] => 8938
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[pdf_file] => patents/07/504/07504342.pdf
[firstpage_image] =>[orig_patent_app_number] => 10210109
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/210109 | Photolithography method for fabricating thin film | Aug 1, 2002 | Issued |
Array
(
[id] => 6408796
[patent_doc_number] => 20020182812
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-05
[patent_title] => 'Transistor structures, methods of incorporating nitrogen into silicon-oxide-containing layers; and methods of forming transistors'
[patent_app_type] => new
[patent_app_number] => 10/205235
[patent_app_country] => US
[patent_app_date] => 2002-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2510
[patent_no_of_claims] => 47
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[pdf_file] => publications/A1/0182/20020182812.pdf
[firstpage_image] =>[orig_patent_app_number] => 10205235
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/205235 | Transistor structures, methods of incorporating nitrogen into silicon-oxide-containing layers; and methods of forming transistors | Jul 25, 2002 | Issued |
Array
(
[id] => 6785789
[patent_doc_number] => 20030137028
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-24
[patent_title] => 'Semiconductor integrated circuit device and method of manufacturing the same'
[patent_app_type] => new
[patent_app_number] => 10/199176
[patent_app_country] => US
[patent_app_date] => 2002-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 74
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0137/20030137028.pdf
[firstpage_image] =>[orig_patent_app_number] => 10199176
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/199176 | Semiconductor integrated circuit device and method of manufacturing the same | Jul 21, 2002 | Issued |
Array
(
[id] => 712348
[patent_doc_number] => 07057294
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-06-06
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/193328
[patent_app_country] => US
[patent_app_date] => 2002-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/07/057/07057294.pdf
[firstpage_image] =>[orig_patent_app_number] => 10193328
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/193328 | Semiconductor device | Jul 11, 2002 | Issued |
Array
(
[id] => 7427304
[patent_doc_number] => 20040007724
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-01-15
[patent_title] => 'Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby'
[patent_app_type] => new
[patent_app_number] => 10/194506
[patent_app_country] => US
[patent_app_date] => 2002-07-12
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[pdf_file] => publications/A1/0007/20040007724.pdf
[firstpage_image] =>[orig_patent_app_number] => 10194506
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/194506 | Process for ultra-thin body SOI devices that incorporate EPI silicon tips and article made thereby | Jul 11, 2002 | Issued |
Array
(
[id] => 1280903
[patent_doc_number] => 06642092
[patent_country] => US
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[patent_issue_date] => 2003-11-04
[patent_title] => 'Thin-film transistors formed on a metal foil substrate'
[patent_app_type] => B1
[patent_app_number] => 10/194895
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[pdf_file] => patents/06/642/06642092.pdf
[firstpage_image] =>[orig_patent_app_number] => 10194895
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/194895 | Thin-film transistors formed on a metal foil substrate | Jul 10, 2002 | Issued |
Array
(
[id] => 6635799
[patent_doc_number] => 20030006490
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[firstpage_image] =>[orig_patent_app_number] => 10188748
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/188748 | Semiconductor integrated circuit device | Jul 4, 2002 | Issued |
Array
(
[id] => 1248156
[patent_doc_number] => 06673649
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-06
[patent_title] => 'Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages'
[patent_app_type] => B1
[patent_app_number] => 10/190019
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/190019 | Microelectronic device packages and methods for controlling the disposition of non-conductive materials in such packages | Jul 4, 2002 | Issued |
Array
(
[id] => 1264425
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[patent_title] => 'Double planar gated SOI MOSFET structure'
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[firstpage_image] =>[orig_patent_app_number] => 10064318
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/064318 | Double planar gated SOI MOSFET structure | Jul 1, 2002 | Issued |
Array
(
[id] => 756203
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[patent_title] => 'Bipolar transistor device and method for fabricating the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/184999 | Bipolar transistor device and method for fabricating the same | Jun 30, 2002 | Issued |
Array
(
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Array
(
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[patent_title] => 'Dual damascene circuit with upper wiring and interconnect line positioned in regions formed as two layers including organic polymer layer and low-permittivity layer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/177667 | Dual damascene circuit with upper wiring and interconnect line positioned in regions formed as two layers including organic polymer layer and low-permittivity layer | Jun 23, 2002 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/177947 | Electronic package having integrated cooling element with clearance for engaging package | Jun 19, 2002 | Issued |
Array
(
[id] => 5787416
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[patent_title] => 'Semiconductor integrated circuit device and process for manufacturing the same'
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[firstpage_image] =>[orig_patent_app_number] => 10173159
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/173159 | Method of forming a ruthenium film by CVD | Jun 17, 2002 | Issued |