
Lauren Nguyen
Examiner (ID: 5733, Phone: (571)270-1428 , Office: P/2871 )
| Most Active Art Unit | 2871 |
| Art Unit(s) | 2871 |
| Total Applications | 1217 |
| Issued Applications | 591 |
| Pending Applications | 144 |
| Abandoned Applications | 499 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 10583489
[patent_doc_number] => 09305613
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-05
[patent_title] => 'Reconfigurable load-reduced memory buffer'
[patent_app_type] => utility
[patent_app_number] => 14/173221
[patent_app_country] => US
[patent_app_date] => 2014-02-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3198
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14173221
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/173221 | Reconfigurable load-reduced memory buffer | Feb 4, 2014 | Issued |
Array
(
[id] => 10582810
[patent_doc_number] => 09304934
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-05
[patent_title] => 'Register file having a plurality of sub-register files'
[patent_app_type] => utility
[patent_app_number] => 14/157805
[patent_app_country] => US
[patent_app_date] => 2014-01-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 14625
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157805
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/157805 | Register file having a plurality of sub-register files | Jan 16, 2014 | Issued |
Array
(
[id] => 9974188
[patent_doc_number] => 09021225
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-28
[patent_title] => 'Dynamic address translation with fetch protection in an emulated environment'
[patent_app_type] => utility
[patent_app_number] => 14/144664
[patent_app_country] => US
[patent_app_date] => 2013-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 23365
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 357
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14144664
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/144664 | Dynamic address translation with fetch protection in an emulated environment | Dec 30, 2013 | Issued |
Array
(
[id] => 10301288
[patent_doc_number] => 20150186287
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'Using Memory System Programming Interfacing'
[patent_app_type] => utility
[patent_app_number] => 14/143413
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 21718
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143413
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/143413 | Using Memory System Programming Interfacing | Dec 29, 2013 | Abandoned |
Array
(
[id] => 10301274
[patent_doc_number] => 20150186274
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'Memory System Cache Eviction Policies'
[patent_app_type] => utility
[patent_app_number] => 14/143339
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 21784
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143339
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/143339 | Memory system cache eviction policies | Dec 29, 2013 | Issued |
Array
(
[id] => 12256098
[patent_doc_number] => 09928245
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-03-27
[patent_title] => 'Method and apparatus for managing memory space'
[patent_app_type] => utility
[patent_app_number] => 14/143312
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5238
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143312
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/143312 | Method and apparatus for managing memory space | Dec 29, 2013 | Issued |
Array
(
[id] => 10948504
[patent_doc_number] => 20140351525
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-27
[patent_title] => 'Efficient method for memory accesses in a multi-core processor'
[patent_app_type] => utility
[patent_app_number] => 14/143252
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5998
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143252
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/143252 | Efficient method for memory accesses in a multi-core processor | Dec 29, 2013 | Issued |
Array
(
[id] => 10301286
[patent_doc_number] => 20150186286
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'Providing Memory System Programming Interfacing'
[patent_app_type] => utility
[patent_app_number] => 14/143397
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 21776
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143397
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/143397 | Providing memory system programming interfacing | Dec 29, 2013 | Issued |
Array
(
[id] => 9954323
[patent_doc_number] => 09003134
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-04-07
[patent_title] => 'Emulation of a dynamic address translation with change record override on a machine of another architecture'
[patent_app_type] => utility
[patent_app_number] => 14/143211
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 23484
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 230
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143211
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/143211 | Emulation of a dynamic address translation with change record override on a machine of another architecture | Dec 29, 2013 | Issued |
Array
(
[id] => 10301074
[patent_doc_number] => 20150186074
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-07-02
[patent_title] => 'Storage Module and Method for Configuring Command Attributes'
[patent_app_type] => utility
[patent_app_number] => 14/143223
[patent_app_country] => US
[patent_app_date] => 2013-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5186
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14143223
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/143223 | Storage module and method for configuring command attributes | Dec 29, 2013 | Issued |
Array
(
[id] => 9947495
[patent_doc_number] => 08996823
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-31
[patent_title] => 'Parallel access virtual tape library and drives'
[patent_app_type] => utility
[patent_app_number] => 14/139414
[patent_app_country] => US
[patent_app_date] => 2013-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6153
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 238
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139414
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/139414 | Parallel access virtual tape library and drives | Dec 22, 2013 | Issued |
Array
(
[id] => 9563750
[patent_doc_number] => 20140181463
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-06-26
[patent_title] => 'Dynamic Address Translation with Translation Table Entry Format Control for Identifying Format of the Translation Table Entry'
[patent_app_type] => utility
[patent_app_number] => 14/133796
[patent_app_country] => US
[patent_app_date] => 2013-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 23283
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133796
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/133796 | Dynamic address translation with translation table entry format control for identifying format of the translation table entry | Dec 18, 2013 | Issued |
Array
(
[id] => 11637640
[patent_doc_number] => 09659621
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-05-23
[patent_title] => 'Semiconductor memory and memory system including the semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 14/100387
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 20
[patent_no_of_words] => 10707
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 309
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100387
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100387 | Semiconductor memory and memory system including the semiconductor memory | Dec 8, 2013 | Issued |
Array
(
[id] => 10536685
[patent_doc_number] => 09262316
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-02-16
[patent_title] => 'Recording dwell time in a non-volatile memory system'
[patent_app_type] => utility
[patent_app_number] => 14/100122
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 9536
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100122
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100122 | Recording dwell time in a non-volatile memory system | Dec 8, 2013 | Issued |
Array
(
[id] => 10275865
[patent_doc_number] => 20150160862
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'MEMORY ARRANGEMENT FOR IMPLEMENTATION OF HIGH-THROUGHPUT KEY-VALUE STORES'
[patent_app_type] => utility
[patent_app_number] => 14/100250
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7543
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100250
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100250 | Memory arrangement for implementation of high-throughput key-value stores | Dec 8, 2013 | Issued |
Array
(
[id] => 10582812
[patent_doc_number] => 09304936
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-04-05
[patent_title] => 'Bypassing a store-conditional request around a store queue'
[patent_app_type] => utility
[patent_app_number] => 14/100356
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6400
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100356
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100356 | Bypassing a store-conditional request around a store queue | Dec 8, 2013 | Issued |
Array
(
[id] => 11780819
[patent_doc_number] => 09390003
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-07-12
[patent_title] => 'Retirement of physical memory based on dwell time'
[patent_app_type] => utility
[patent_app_number] => 14/100138
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 9520
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 121
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100138
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100138 | Retirement of physical memory based on dwell time | Dec 8, 2013 | Issued |
Array
(
[id] => 10276039
[patent_doc_number] => 20150161036
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'PROGRAMMING NON-VOLATILE MEMORY USING A RELAXED DWELL TIME'
[patent_app_type] => utility
[patent_app_number] => 14/100172
[patent_app_country] => US
[patent_app_date] => 2013-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9520
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14100172
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/100172 | Programming non-volatile memory using a relaxed dwell time | Dec 8, 2013 | Issued |
Array
(
[id] => 10275894
[patent_doc_number] => 20150160891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-06-11
[patent_title] => 'SYSTEM AND METHOD FOR DYNAMICALLY LOAD BALANCING STORAGE MEDIA DEVICES BASED ON A MINIMUM PERFORMANCE LEVEL'
[patent_app_type] => utility
[patent_app_number] => 14/099820
[patent_app_country] => US
[patent_app_date] => 2013-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5216
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14099820
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/099820 | SYSTEM AND METHOD FOR DYNAMICALLY LOAD BALANCING STORAGE MEDIA DEVICES BASED ON A MINIMUM PERFORMANCE LEVEL | Dec 5, 2013 | Abandoned |
Array
(
[id] => 14061607
[patent_doc_number] => 10235096
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-19
[patent_title] => System and method for dynamically load balancing storage media devices based on an average or discounted average sustained performance level
[patent_app_type] => utility
[patent_app_number] => 14/099846
[patent_app_country] => US
[patent_app_date] => 2013-12-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 4719
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 213
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14099846
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/099846 | System and method for dynamically load balancing storage media devices based on an average or discounted average sustained performance level | Dec 5, 2013 | Issued |