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Lawrence Baranyai

Examiner (ID: 12458)

Most Active Art Unit
2665
Art Unit(s)
2665
Total Applications
1
Issued Applications
1
Pending Applications
0
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16651892 [patent_doc_number] => 10929067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Nonvolatile memory system and method for controlling write and read operations in the nonvolatile memory by a host [patent_app_type] => utility [patent_app_number] => 16/564412 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 15619 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564412 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564412
Nonvolatile memory system and method for controlling write and read operations in the nonvolatile memory by a host Sep 8, 2019 Issued
Array ( [id] => 16942771 [patent_doc_number] => 11055010 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-07-06 [patent_title] => Data partition migration via metadata transfer and access attribute change [patent_app_type] => utility [patent_app_number] => 16/561985 [patent_app_country] => US [patent_app_date] => 2019-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16561985 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/561985
Data partition migration via metadata transfer and access attribute change Sep 4, 2019 Issued
Array ( [id] => 16675484 [patent_doc_number] => 20210064250 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => PREPARING A DATA STORAGE SYSTEM FOR MAINTENANCE OPERATIONS [patent_app_type] => utility [patent_app_number] => 16/559366 [patent_app_country] => US [patent_app_date] => 2019-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9268 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16559366 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/559366
Determining an optimal maintenance time for a data storage system utilizing historical data Sep 2, 2019 Issued
Array ( [id] => 16675760 [patent_doc_number] => 20210064526 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => REMAPPING TECHNIQUES FOR NAND STORAGE [patent_app_type] => utility [patent_app_number] => 16/552246 [patent_app_country] => US [patent_app_date] => 2019-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9061 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16552246 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/552246
Remapping techniques for a range of logical block addresses in a logical to physical table of NAND storage Aug 26, 2019 Issued
Array ( [id] => 17076814 [patent_doc_number] => 11113214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-09-07 [patent_title] => Controlling data transfers between a tier of persistent data storage and processor memory with a high-speed fabric controller [patent_app_type] => utility [patent_app_number] => 16/550004 [patent_app_country] => US [patent_app_date] => 2019-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6842 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550004 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/550004
Controlling data transfers between a tier of persistent data storage and processor memory with a high-speed fabric controller Aug 22, 2019 Issued
Array ( [id] => 17164954 [patent_doc_number] => 11151053 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Increasing data read and/or write heat tracking resolution in storage devices having cache architecture [patent_app_type] => utility [patent_app_number] => 16/534834 [patent_app_country] => US [patent_app_date] => 2019-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 14013 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16534834 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/534834
Increasing data read and/or write heat tracking resolution in storage devices having cache architecture Aug 6, 2019 Issued
Array ( [id] => 17352271 [patent_doc_number] => 11226908 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-01-18 [patent_title] => Securing transactions involving protected memory regions having different permission levels [patent_app_type] => utility [patent_app_number] => 16/528559 [patent_app_country] => US [patent_app_date] => 2019-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6168 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16528559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/528559
Securing transactions involving protected memory regions having different permission levels Jul 30, 2019 Issued
Array ( [id] => 17636678 [patent_doc_number] => 11347402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-31 [patent_title] => Performing wear leveling operations in a memory based on block cycles and use of spare blocks [patent_app_type] => utility [patent_app_number] => 16/523860 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4082 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523860 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523860
Performing wear leveling operations in a memory based on block cycles and use of spare blocks Jul 25, 2019 Issued
Array ( [id] => 17408797 [patent_doc_number] => 11249678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-15 [patent_title] => Serial memory device single-bit or plurality-bit serial I/O mode selection [patent_app_type] => utility [patent_app_number] => 16/523429 [patent_app_country] => US [patent_app_date] => 2019-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7168 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523429 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/523429
Serial memory device single-bit or plurality-bit serial I/O mode selection Jul 25, 2019 Issued
Array ( [id] => 16551799 [patent_doc_number] => 10884959 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-05 [patent_title] => Way partitioning for a system-level cache [patent_app_type] => utility [patent_app_number] => 16/518503 [patent_app_country] => US [patent_app_date] => 2019-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9091 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16518503 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/518503
Way partitioning for a system-level cache Jul 21, 2019 Issued
Array ( [id] => 15967077 [patent_doc_number] => 20200167290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => MEMORY CONTROLLER, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD OF THE MEMORY CONTROLLER [patent_app_type] => utility [patent_app_number] => 16/446912 [patent_app_country] => US [patent_app_date] => 2019-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16446912 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/446912
Memory controller including address translation module, memory system including the memory controller, and operating method of the memory controller Jun 19, 2019 Issued
Array ( [id] => 14901131 [patent_doc_number] => 20190294331 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => DATA WRITING PROCESSING INTO MEMORY OF A SEMICONDUCTOR MEMORY DEVICE BY USING A MEMORY OF A HOST DEVICE [patent_app_type] => utility [patent_app_number] => 16/440172 [patent_app_country] => US [patent_app_date] => 2019-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16440172 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/440172
Memory system with block rearrangement to secure a free block based on read valid first and second data Jun 12, 2019 Issued
Array ( [id] => 14901125 [patent_doc_number] => 20190294328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => VIRTUALIZING NON-VOLATILE STORAGE AT A PERIPHERAL DEVICE [patent_app_type] => utility [patent_app_number] => 16/435372 [patent_app_country] => US [patent_app_date] => 2019-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9966 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435372 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/435372
Suspend, restart and resume to update storage virtualization at a peripheral device Jun 6, 2019 Issued
Array ( [id] => 14872573 [patent_doc_number] => 20190286528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SYSTEM AND METHOD FOR MANAGING AND PRODUCING A DATASET IMAGE ACROSS MULTIPLE STORAGE SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/429463 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429463 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/429463
System and method for utilizing operation identifiers for communicating with storage systems to perform a dataset image operation Jun 2, 2019 Issued
Array ( [id] => 14872575 [patent_doc_number] => 20190286529 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-19 [patent_title] => SYSTEM AND METHOD FOR MANAGING AND PRODUCING A DATASET IMAGE ACROSS MULTIPLE STORAGE SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/429475 [patent_app_country] => US [patent_app_date] => 2019-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17139 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16429475 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/429475
System and method for enforcing a dataset timeout for generating a dataset image Jun 2, 2019 Issued
Array ( [id] => 17394875 [patent_doc_number] => 11243889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Cache architecture for comparing data on a single page [patent_app_type] => utility [patent_app_number] => 16/422589 [patent_app_country] => US [patent_app_date] => 2019-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4860 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16422589 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/422589
Cache architecture for comparing data on a single page May 23, 2019 Issued
Array ( [id] => 16470173 [patent_doc_number] => 20200371710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-26 [patent_title] => MEMORY DEVICE AND ASSOCIATED ACCESS METHOD [patent_app_type] => utility [patent_app_number] => 16/419086 [patent_app_country] => US [patent_app_date] => 2019-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16419086 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/419086
Memory device with multiple physical spaces, multiple non-volatile memory arrays, multiple main data, multiple metadata of multiple types of commands, and access method thereof May 21, 2019 Issued
Array ( [id] => 15902759 [patent_doc_number] => 20200150899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => STORAGE DEVICE, OPERATING METHOD OF STORAGE DEVICE, AND OPERATING METHOD OF HOST CONTROLLING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 16/413755 [patent_app_country] => US [patent_app_date] => 2019-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9197 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16413755 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/413755
Memory systems and methods that allocate memory banks using striping size and stream identification information contained within directive commands May 15, 2019 Issued
Array ( [id] => 14750825 [patent_doc_number] => 20190258586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-22 [patent_title] => Logical Device Mobility in a Scale Out Storage System [patent_app_type] => utility [patent_app_number] => 16/402635 [patent_app_country] => US [patent_app_date] => 2019-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402635 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/402635
Device access point mobility in a scale out storage system May 2, 2019 Issued
Array ( [id] => 15090163 [patent_doc_number] => 20190339892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => MEMORY MANAGEMENT SYSTEM AND MEMORY MANAGEMENT METHOD FOR DYNAMIC MEMORY MANAGEMENT [patent_app_type] => utility [patent_app_number] => 16/402198 [patent_app_country] => US [patent_app_date] => 2019-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16402198 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/402198
Memory management system and memory management method for dynamic memory management by monitoring whether memory is accessed and predicting when memory is to be accessed May 1, 2019 Issued
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