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Lawrence Baranyai

Examiner (ID: 12458)

Most Active Art Unit
2665
Art Unit(s)
2665
Total Applications
1
Issued Applications
1
Pending Applications
0
Abandoned Applications
0

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16278957 [patent_doc_number] => 10761988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => Methods and apparatus of cache access to a data array with locality-dependent latency characteristics [patent_app_type] => utility [patent_app_number] => 16/142330 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4963 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142330 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/142330
Methods and apparatus of cache access to a data array with locality-dependent latency characteristics Sep 25, 2018 Issued
Array ( [id] => 15500421 [patent_doc_number] => 20200050399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => DATA MERGE METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 16/141990 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16141990 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/141990
Data merge method which reads first physical unit twice for respectively performing first stage programming operation and second stage programming operation on second physical unit, memory storage device and memory control circuit unit Sep 25, 2018 Issued
Array ( [id] => 15685487 [patent_doc_number] => 20200097407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-26 [patent_title] => PRODUCER/CONSUMER DATA TRANSFER WITHIN A DATA PROCESSING SYSTEM HAVING A CACHE [patent_app_type] => utility [patent_app_number] => 16/142178 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16142178 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/142178
Producer/consumer paced data transfer within a data processing system having a cache which implements different cache coherency protocols Sep 25, 2018 Issued
Array ( [id] => 14218687 [patent_doc_number] => 20190121728 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-25 [patent_title] => MEMORY DEVICE WITH DYNAMIC GARBAGE COLLECTION AND METHOD OF DYNAMIC GARBAGE COLLECTION FOR A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/134849 [patent_app_country] => US [patent_app_date] => 2018-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9871 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16134849 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/134849
Method of dynamic garbage collection for a memory device based on valid page count (VPC), garbage collection speed, and maximum and minimum operating speeds Sep 17, 2018 Issued
Array ( [id] => 15789185 [patent_doc_number] => 10628317 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-04-21 [patent_title] => System and method for caching data in a virtual storage environment based on the clustering of related data blocks [patent_app_type] => utility [patent_app_number] => 16/129993 [patent_app_country] => US [patent_app_date] => 2018-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7835 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16129993 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/129993
System and method for caching data in a virtual storage environment based on the clustering of related data blocks Sep 12, 2018 Issued
Array ( [id] => 14076935 [patent_doc_number] => 20190087355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => MEMORY ACCESS CONTROL USING ADDRESS ALIASING [patent_app_type] => utility [patent_app_number] => 16/130858 [patent_app_country] => US [patent_app_date] => 2018-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16130858 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/130858
Memory access control and verification using address aliasing and markers Sep 12, 2018 Issued
Array ( [id] => 16355087 [patent_doc_number] => 10795597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-06 [patent_title] => Thinly provisioned disk drives with zone provisioning and compression in relation to zone granularity [patent_app_type] => utility [patent_app_number] => 16/128203 [patent_app_country] => US [patent_app_date] => 2018-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16128203 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/128203
Thinly provisioned disk drives with zone provisioning and compression in relation to zone granularity Sep 10, 2018 Issued
Array ( [id] => 16566629 [patent_doc_number] => 10892003 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes [patent_app_type] => utility [patent_app_number] => 16/116751 [patent_app_country] => US [patent_app_date] => 2018-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4330 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16116751 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/116751
Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes Aug 28, 2018 Issued
Array ( [id] => 13797101 [patent_doc_number] => 20190012089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-10 [patent_title] => INTERCONNECT SYSTEMS AND METHODS USING MEMORY LINKS TO SEND PACKETIZED DATA OVER DIFFERENT ENDPOINTS OF A DATA HANDLING DEVICE [patent_app_type] => utility [patent_app_number] => 16/109327 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7441 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109327 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/109327
Interconnect systems and methods using memory links to send packetized data between different data handling devices of different memory domains Aug 21, 2018 Issued
Array ( [id] => 16278745 [patent_doc_number] => 10761775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-01 [patent_title] => System and method for NVMe inter command association in SSD storage using a bridge device [patent_app_type] => utility [patent_app_number] => 16/107969 [patent_app_country] => US [patent_app_date] => 2018-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8380 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16107969 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/107969
System and method for NVMe inter command association in SSD storage using a bridge device Aug 20, 2018 Issued
Array ( [id] => 15399239 [patent_doc_number] => 10540276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Method of processing data based on erase operations of logical pages related to data compression rate of mapping table in data storage device [patent_app_type] => utility [patent_app_number] => 16/039787 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6679 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039787 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/039787
Method of processing data based on erase operations of logical pages related to data compression rate of mapping table in data storage device Jul 18, 2018 Issued
Array ( [id] => 14107291 [patent_doc_number] => 20190095321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => Data Storage Device and Method for Writing Data into a Memory Device of a Data Storage Device [patent_app_type] => utility [patent_app_number] => 16/039740 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039740 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/039740
Backup mechanism of writing sequential data to single-level cell buffer and multi-level cell buffer Jul 18, 2018 Issued
Array ( [id] => 16185922 [patent_doc_number] => 10719254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Merging data from single-level cell block to multiple-level cell block based on sudden power off event and valid page count in single-level cell block [patent_app_type] => utility [patent_app_number] => 16/039722 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7389 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16039722 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/039722
Merging data from single-level cell block to multiple-level cell block based on sudden power off event and valid page count in single-level cell block Jul 18, 2018 Issued
Array ( [id] => 16145713 [patent_doc_number] => 10705927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-07 [patent_title] => Freeze a volume of a replication set and unfreeze the volume based on at least one of a snapshot permit message, a snapshot abort message, and expiration of a timeout [patent_app_type] => utility [patent_app_number] => 16/040129 [patent_app_country] => US [patent_app_date] => 2018-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7617 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16040129 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/040129
Freeze a volume of a replication set and unfreeze the volume based on at least one of a snapshot permit message, a snapshot abort message, and expiration of a timeout Jul 18, 2018 Issued
Array ( [id] => 16408859 [patent_doc_number] => 10817412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-27 [patent_title] => Methods for migrating information stored in memory using an intermediate depth map [patent_app_type] => utility [patent_app_number] => 16/030600 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9271 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030600 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/030600
Methods for migrating information stored in memory using an intermediate depth map Jul 8, 2018 Issued
Array ( [id] => 17194734 [patent_doc_number] => 11163487 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Methods for generating notifications for updated information from mode registers of a memory device to a host and memory devices and systems employing the same [patent_app_type] => utility [patent_app_number] => 16/029269 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4673 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029269 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029269
Methods for generating notifications for updated information from mode registers of a memory device to a host and memory devices and systems employing the same Jul 5, 2018 Issued
Array ( [id] => 15472391 [patent_doc_number] => 10552069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-02-04 [patent_title] => Caching the topology of a distributed data storage system [patent_app_type] => utility [patent_app_number] => 16/029454 [patent_app_country] => US [patent_app_date] => 2018-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 10754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029454 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029454
Caching the topology of a distributed data storage system Jul 5, 2018 Issued
Array ( [id] => 15297563 [patent_doc_number] => 20190391917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => SHALLOW CACHE FOR CONTENT REPLICATION [patent_app_type] => utility [patent_app_number] => 16/017985 [patent_app_country] => US [patent_app_date] => 2018-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16017985 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/017985
Shallow cache for content replication Jun 24, 2018 Issued
Array ( [id] => 17252985 [patent_doc_number] => 11188474 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-30 [patent_title] => Balanced caching between a cache and a non-volatile memory based on rates corresponding to the cache and the non-volatile memory [patent_app_type] => utility [patent_app_number] => 16/012607 [patent_app_country] => US [patent_app_date] => 2018-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16012607 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/012607
Balanced caching between a cache and a non-volatile memory based on rates corresponding to the cache and the non-volatile memory Jun 18, 2018 Issued
Array ( [id] => 15059071 [patent_doc_number] => 10459841 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Information processing apparatus, information processing system, and method of controlling information processing apparatus, configured to form ring-shaped bus [patent_app_type] => utility [patent_app_number] => 16/008095 [patent_app_country] => US [patent_app_date] => 2018-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6147 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16008095 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/008095
Information processing apparatus, information processing system, and method of controlling information processing apparatus, configured to form ring-shaped bus Jun 13, 2018 Issued
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